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At a Glance
512 Pages
Revised
23.4 x 19.1 x 3.18
Paperback
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See MIPS Run, Second Edition, is not only a thorough update of the first edition, it is also a marriage of the best-known RISC architecture--MIPS--with the best-known open-source OS--Linux. The first part of the book begins with MIPS design principles and then describes the MIPS instruction set and programmers' resources. It uses the MIPS32 standard as a baseline (the 1st edition used the R3000) from which to compare all other versions of the architecture and assumes that MIPS64 is the main option. The second part is a significant change from the first edition. It provides concrete examples of operating system low level code, by using Linux as the example operating system. It describes how Linux is built on the foundations the MIPS hardware provides and summarizes the Linux application environment, describing the libraries, kernel device-drivers and CPU-specific code. It then digs deep into application code and library support, protection and memory management, interrupts in the Linux kernel and multiprocessor Linux.
Sweetman has revised his best-selling MIPS bible for MIPS programmers, embedded systems designers, developers and programmers, who need an in-depth understanding of the MIPS architecture and specific guidance for writing software for MIPS-based systems, which are increasingly Linux-based.
- Completely new material offers the best explanation available on how Linux runs on real hardware
- Provides a complete, updated and easy-to-use guide to the MIPS instruction set using the MIPS32 standard as the baseline architecture with the MIPS64 as the main option
- Retains the same engaging writing style that made the first edition so readable, reflecting the authors 20+ years experience in designing systems based on the MIPS architecture
Industry Reviews
Foreword | p. v |
Preface | p. xv |
Style and Limits | p. xviii |
Conventions | p. xviii |
Acknowledgments | p. xix |
RISCs and MIPS Architectures | p. 1 |
Pipelines | p. 2 |
What Makes a Pipeline Inefficient? | p. 3 |
The Pipeline and Caching | p. 4 |
The MIPS Five-Stage Pipeline | p. 5 |
RISC and CISC | p. 7 |
Great MIPS Chips of the Past and Present | p. 8 |
R2000 to R3000 Processors | p. 8 |
The R6000 Processor: A Diversion | p. 9 |
The First CPU Cores | p. 11 |
The R4000 Processor: A Revolution | p. 12 |
The Rise and Fall of the ACE Consortium | p. 12 |
SGI Acquires MIPS | p. 13 |
QED: Fast MIPS Processors for Embedded Systems | p. 13 |
The R10000 Processor and its Successors | p. 14 |
MIPS Processors in Consumer Electronics | p. 15 |
MIPS in Network Routers and Laser Printers | p. 15 |
MIPS Processors in Modern Times | p. 17 |
The Rebirth of MIPS Technologies | p. 20 |
The Present Day | p. 21 |
MIPS Compared with CISC Architectures | p. 23 |
Constraints on MIPS Instructions | p. 23 |
Addressing and Memory Accesses | p. 24 |
Features You Won't Find | p. 25 |
Programmer-Visible Pipeline Effects | p. 27 |
MIPS Architecture | p. 29 |
A Flavor of MIPS Assembly Language | p. 33 |
Registers | p. 34 |
Conventional Names and Uses of General-Purpose Registers | p. 35 |
Integer Multiply Unit and Registers | p. 38 |
Loading and Storing: Addressing Modes | p. 39 |
Data Types in Memory and Registers | p. 39 |
Integer Data Types | p. 39 |
Unaligned Loads and Stores | p. 40 |
Floating-Point Data in Memory | p. 41 |
Synthesized Instructions in Assembly Language | p. 42 |
MIPS I to MIPS64 ISAs: 64-Bit (and Other) Extensions | p. 43 |
To 64 Bits | p. 45 |
Who Needs 64 Bits? | p. 45 |
Regarding 64 Bits and No Mode Switch: Data in Registers | p. 46 |
Basic Address Space | p. 47 |
Addressing in Simple Systems | p. 49 |
Kernel versus User Privilege Level | p. 49 |
The Pull Picture: The 64-Bit View of the Memory Map | p. 50 |
Pipeline Visibility | p. 50 |
Coprocessor 0: MIPS Processor Control | p. 53 |
CPU Control Instructions | p. 55 |
Which Registers Are Relevant When? | p. 58 |
CPU Control Registers and Their Encoding | p. 59 |
Status Register (SR) | p. 60 |
Cause Register | p. 64 |
Exception Restart Address (EPC) Register | p. 65 |
Bad Virtual Address (BadVAddr) Register | p. 67 |
Count/Compare Registers: The On-CPU Timer | p. 68 |
Processor ID (PRId) Register | p. 68 |
Config Registers: CPU Resource Information and Configuration | p. 69 |
EBase and IntCtl: Interrupt and Exception Setup | p. 73 |
SRSCtl and SRSMap: Shadow Register Setup | p. 74 |
Load-Linked Address (LLAddr) Register | p. 75 |
CP0 Hazards-A Trap for the Unwary | p. 75 |
Hazard Barrier Instructions | p. 76 |
Instruction Hazards and User Hazards | p. 77 |
Hazards between CP0 Instructions | p. 77 |
How Caches Work on MIPS Processors | p. 79 |
Caches and Cache Management | p. 79 |
How Caches Work | p. 80 |
Write-Through Caches in Early MIPS CPUs | p. 83 |
Write-Back Caches in MIPS CPUs | p. 84 |
Other Choices in Cache Design | p. 84 |
Managing Caches | p. 86 |
L2 and L3 Caches | p. 88 |
Cache Configurations for MIPS CPUs | p. 88 |
Programming MIPS32/64 Caches | p. 90 |
The Cache Instruction | p. 91 |
Cache Initialization and Tag/Data Registers | p. 92 |
CacheErr, ERR, and ErrorEPC Registers: Memory/Cache Error Handling | p. 94 |
Cache Sizing and Figuring Out Configuration | p. 95 |
Initialization Routines | p. 96 |
Invalidating or Writing Back a Region of Memory in the Cache | p. 97 |
Cache Efficiency | p. 98 |
Reorganizing Software to Influence Cache Efficiency | p. 100 |
Cache Aliases | p. 102 |
Exceptions, Interrupts, and Initialization | p. 105 |
Precise Exceptions | p. 107 |
Nonprecise Exceptions-The Multiplier in Historic MIPS CPUs | p. 108 |
When Exceptions Happen | p. 109 |
Exception Vectors: Where Exception Handling Starts | p. 109 |
Exception Handling: Basics | p. 113 |
Returning from an Exception | p. 114 |
Nesting Exceptions | p. 114 |
An Exception Routine | p. 115 |
Interrupts | p. 115 |
Interrupt Resources in MIPS CPUs | p. 116 |
Implementing Interrupt Priority in Software | p. 118 |
Atomicity and Atomic Changes to SR | p. 120 |
Critical Regions with Interrupts Enabled: Semaphores the MIPS Way | p. 121 |
Vectored and EIC Interrupts in MIPS32/64 CPUs | p. 123 |
Shadow Registers | p. 124 |
Starting Up | p. 124 |
Probing and Recognizing Your CPU | p. 126 |
Bootstrap Sequences | p. 127 |
Starting Up an Application | p. 128 |
Emulating Instructions | p. 128 |
Low-level Memory Management and the TLB | p. 131 |
The TLB/MMU Hardware and What It Does | p. 131 |
TLB/MMU Registers Described | p. 132 |
TLB Key Fields-EntryHi and PageMask | p. 134 |
TLB Output Fields-EntryLoO-1 | p. 136 |
Selecting a TLB Entry-Index, Random, and Wired Registers | p. 137 |
Page-Table Access Helpers-Context and XContext | p. 138 |
TLB/MMU Control Instructions | p. 140 |
Programming the TLB | p. 141 |
How Refill Happens | p. 142 |
Using ASIDs | p. 143 |
The Random Register and Wired Entries | p. 143 |
Hardware-Friendly Page Tables and Refill Mechanism | p. 143 |
TLB Miss Handling | p. 145 |
XTLB Miss Handler | p. 146 |
Everyday Use of the MIPS TLB | p. 147 |
Memory Management in a Simpler OS | p. 149 |
Floating-Point Support | p. 151 |
A Basic Description of Floating Point | p. 151 |
The IEEE 754 Standard and Its Background | p. 152 |
How IEEE Floating-Point Numbers Are Stored | p. 154 |
IEEE Mantissa and Normalization | p. 155 |
Reserved Exponent Values for Use with Strange Values | p. 155 |
MIPS FP Data Formats | p. 156 |
MIPS Implementation of IEEE 754 | p. 158 |
Need for FP Trap Handler and Emulator in All MIPS CPUs | p. 159 |
Floating-Point Registers | p. 159 |
Conventional Names and Uses of Floating-Point Registers | p. 160 |
Floating-Point Exceptions/Interrupts | p. 161 |
Floating-Point Control: The Control/Status Register | p. 161 |
Floating-Point Implementation Register | p. 165 |
Guide to FP Instructions | p. 166 |
Load/Store | p. 167 |
Move between Registers | p. 168 |
Three-Operand Arithmetic Operations | p. 169 |
Multiply-Add Operations | p. 170 |
Unary (Sign-Changing) Operations | p. 170 |
Conversion Operations | p. 170 |
Conditional Branch and Test Instructions | p. 171 |
Paired-Single Floating-Point Instructions and the MIPS-3D ASE | p. 173 |
Exceptions on Paired-Single Instructions | p. 174 |
Paired-Single Three-Operand Arithmetic, Multiply-Add, Sign-Changing, and Nonconditional Move Operations | p. 174 |
Paired-Single Conversion Operations | p. 175 |
Paired-Single Test and Conditional Move Instructions | p. 176 |
MIPS-3D Instructions | p. 176 |
Instruction Timing Requirements | p. 179 |
Instruction Timing for Speed | p. 179 |
Initialization and Enabling on Demand | p. 180 |
Floating-Point Emulation | p. 181 |
Complete Guide to the MIPS Instruction Set | p. 183 |
A Simple Example | p. 183 |
Assembly Instructions and What They Mean | p. 185 |
U and Non-U Mnemonics | p. 186 |
Divide Mnemonics | p. 187 |
Inventory of Instructions | p. 188 |
Floating-Point Instructions | p. 210 |
Differences in MIPS32/64 Release 1 | p. 216 |
Regular Instructions Added in Release 2 | p. 216 |
Privileged Instructions Added in Release 2 | p. 218 |
Peculiar Instructions and Their Purposes | p. 218 |
Load Left/Load Right: Unaligned Load and Store | p. 218 |
Load-Linked/Store-Conditional | p. 223 |
Conditional Move Instructions | p. 224 |
Branch-Likely | p. 225 |
Integer Multiply-Accumulate and Multiply-Add Instructions | p. 226 |
Floating-Point Multiply-Add Instructions | p. 227 |
Multiple FP Condition Bits | p. 228 |
Prefetch | p. 228 |
Sync: A Memory Barrier for Loads and Stores | p. 229 |
Hazard Barrier Instructions | p. 231 |
Synci: Cache Management for Instruction Writers | p. 232 |
Read Hardware Register | p. 232 |
Instruction Encodings | p. 233 |
Fields in the Instruction Encoding Table | p. 233 |
Notes on the Instruction Encoding Table | p. 251 |
Encodings and Simple Implementation | p. 251 |
Instructions by Functional Group | p. 252 |
No-op | p. 252 |
Register/Register Moves | p. 252 |
Load Constant | p. 253 |
Arithmetical/Logical | p. 253 |
Integer Multiply, Divide, and Remainder | p. 255 |
Integer Multiply-Accumulate | p. 256 |
Loads and Stores | p. 257 |
Jumps, Subroutine Calls, and Branches | p. 259 |
Breakpoint and Trap | p. 260 |
CP0 Functions | p. 260 |
Floating Point | p. 261 |
Limited User-Mode Access to "Under the Hood" Features | p. 261 |
Reading MIPS Assembly Language | p. 263 |
A Simple Example | p. 264 |
Syntax Overview | p. 268 |
Layout, Delimiters, and Identifiers | p. 268 |
General Rules for Instructions | p. 269 |
Computational Instructions: Three-, Two-, and One-Register | p. 269 |
Immediates: Computational Instructions with Constants | p. 270 |
Regarding 64-Bit and 32-Bit Instructions | p. 271 |
Addressing Modes | p. 271 |
Gp-Relative Addressing | p. 273 |
Object File and Memory Layout | p. 274 |
Practical Program Layout, Including Stack and Heap | p. 277 |
Porting Software to the MIPS Architecture | p. 279 |
Low-Level Software for MIPS Applications: A Checklist of Frequently Encountered Problems | p. 280 |
Endianness: Words, Bytes, and Bit Order | p. 281 |
Bits, Bytes, Words, and Integers | p. 281 |
Software and Endianness | p. 284 |
Hardware and Endianness | p. 287 |
Bi-endian Software for a MIPS CPU | p. 293 |
Portability and Endianness-Independent Code | p. 295 |
Endianness and Foreign Data | p. 295 |
Trouble with Visible Caches | p. 296 |
Cache Management and DMA Data | p. 298 |
Cache Management and Writing Instructions: Self-Modifying Code | p. 299 |
Cache Management and Uncached or Write-Through Data | p. 300 |
Cache Aliases and Page Coloring | p. 301 |
Memory Access Ordering and Reordering | p. 301 |
Ordering and Write Buffers | p. 304 |
Implementing wbflush | p. 304 |
Writing it in C | p. 305 |
Wrapping Assembly Code with the GNU C Compiler | p. 305 |
Memory-Mapped I/O Registers and "Volatile" | p. 307 |
Miscellaneous Issues When Writing C for MIPS Applications | p. 308 |
MIPS Software Standards (ABIs) | p. 311 |
Data Representations and Alignment | p. 312 |
Sizes of Basic Types | p. 312 |
Sizes of "long" and Pointer Types | p. 313 |
Alignment Requirements | p. 313 |
Memory Layout of Basic Types and How It Changes with Endianness | p. 313 |
Memory Layout of Structure and Array Types and Alignment | p. 315 |
Bitfields in Structures | p. 315 |
Unaligned Data from C | p. 318 |
Argument Passing and Stack Conventions for MIPS ABIs | p. 319 |
The Stack, Subroutine Linkage, and Parameter Passing | p. 320 |
Stack Argument Structure in o32 | p. 320 |
Using Registers to Pass Arguments | p. 321 |
Examples from the C Library | p. 322 |
An Exotic Example: Passing Structures | p. 323 |
Passing a Variable Number of Arguments | p. 324 |
Returning a Value from a Function | p. 325 |
Evolving Register-Use Standards: SGIs n32 and n64 | p. 326 |
Stack Layouts, Stack Frames, and Helping Debuggers | p. 329 |
Variable Number of Arguments and stdargs | p. 337 |
Debugging MIPS Designs-Debug and Profiling Features | p. 339 |
The "EJTAG" On-chip Debug Unit | p. 341 |
EJTAG History | p. 343 |
How the Probe Controls the CPU | p. 343 |
Debug Communications through JTAG | p. 344 |
Debug Mode | p. 344 |
Single-Stepping | p. 346 |
The dseg Memory Decode Region | p. 346 |
EJTAG CP0 Registers, Particularly Debug | p. 348 |
The DCR (Debug Control) Memory-Mapped Register | p. 351 |
EJTAG Breakpoint Hardware | p. 352 |
Understanding Breakpoint Conditions | p. 355 |
Imprecise Debug Breaks | p. 356 |
PC Sampling with EJTAG | p. 356 |
Using EJTAG without a Probe | p. 356 |
Pre-EJTAG Debug Support-Break Instruction and CP0 Watchpoints | p. 358 |
PDtrace | p. 359 |
Performance Counters | p. 360 |
GNU/Linux from Eight Miles High | p. 363 |
Components | p. 364 |
Layering in the Kernel | p. 368 |
MIPS CPU in Exception Mode | p. 368 |
MIPS CPU with Some or All Interrupts off | p. 369 |
Interrupt Context | p. 370 |
Executing the Kernel in Thread Context | p. 370 |
How Hardware and Software Work Together | p. 371 |
The Life and Times of an Interrupt | p. 371 |
High-Performance Interrupt Handling and Linux | p. 374 |
Threads, Critical Regions, and Atomicity | p. 375 |
MIPS Architecture and Atomic Operations | p. 376 |
Linux Spinlocks | p. 377 |
What Happens on a System Call | p. 378 |
How Addresses Get Translated in Linux/MIPS Systems | p. 380 |
What's Memory Translation For? | p. 382 |
Basic Process Layout and Protection | p. 384 |
Mapping Process Addresses to Real Memory | p. 385 |
Paged Mapping Preferred | p. 386 |
What We Really Want | p. 387 |
Origins of the MIPS Design | p. 389 |
Keeping Track of Modified Pages (Simulating "Dirty" Bits) | p. 392 |
How the Kernel Services a TLB Refill Exception | p. 393 |
Care and Maintenance of the TLB | p. 397 |
Memory Translation and 64-Bit Pointers | p. 397 |
MIPS Specific Issues in the Linux Kernel | p. 399 |
Explicit Cache Management | p. 399 |
DMA Device Accesses | p. 399 |
Writing Instructions for Later Execution | p. 401 |
Cache/Memory Mapping Problems | p. 401 |
Cache Aliases | p. 402 |
CP0 Pipeline Hazards | p. 403 |
Multiprocessor Systems and Coherent Caches | p. 403 |
Demon Tweaks for a Critical Routine | p. 406 |
Linux Application Code, PIC, and Libraries | p. 409 |
How Link Units Get into a Program | p. 411 |
Global Offset Table (GOT) Organization | p. 412 |
MIPS Multithreading | p. 415 |
What Is Multithreading? | p. 415 |
Why Is MT Useful? | p. 417 |
How to Do Multithreading for MIPS | p. 417 |
MT in Action | p. 421 |
Other Optional Extensions to the MIPS Instruction Set | p. 425 |
MIPS16 and MIPS16e ASEs | p. 425 |
Special Encodings and Instructions in the MIPS16 ASE | p. 426 |
The MIPS16 ASE Evaluated | p. 427 |
The MIPS DSP ASE | p. 428 |
The MDMX ASE | p. 429 |
MIPS Glossary | p. 431 |
References | p. 477 |
Books and Articles | p. 477 |
Online Resources | p. 478 |
Index | p. 481 |
Table of Contents provided by Ingram. All Rights Reserved. |
ISBN: 9780120884216
ISBN-10: 0120884216
Series: The Morgan Kaufmann Series in Computer Architecture and Design
Published: 17th October 2006
Format: Paperback
Language: English
Number of Pages: 512
Audience: Professional and Scholarly
Publisher: Morgan Kaufmann Publishing
Country of Publication: US
Edition Number: 2
Edition Type: Revised
Dimensions (cm): 23.4 x 19.1 x 3.18
Weight (kg): 1.03
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