Embedded core processors are becoming a vital part of today's system-on-a-chip in the growing areas of telecommunications, multimedia and consumer electronics. This is mainly in response to a need to track evolving standards with the flexibility of embedded software. Consequently, maintaining the high product performance and low product cost requires a careful design of the processor tuned to the application domain. With the increased presence of instruction-set processors, retargetable software compilation techniques are critical, not only for improving engineering productivity, but to allow designers to explore the architectural possibilities for the application domain.
Retargetable Compilers for Embedded Core Processors, with a Foreword written by Ahmed Jerraya and Pierre Paulin, overviews the techniques of modern retargetable compilers and shows the application of practical techniques to embedded instruction-set processors. The methods are highlighted with examples from industry processors used in products for multimedia, telecommunications, and consumer electronics. An emphasis is given to the methodology and experience gained in applying two different retargetable compiler approaches in industrial settings. The book also discusses many pragmatic areas such as language support, source code abstraction levels, validation strategies, and source-level debugging. In addition, new compiler techniques are described which support address generation for DSP architecture trends. The contribution is an address calculation transformation based on an architectural model.
Retargetable Compilers for Embedded Core Processors will be of interest to embedded system designers and programmers, the developers of electronic design automation (EDA) tools for embedded systems, and researchers in hardware/software co-design.
|List of Figures|
|List of Tables|
|An Overview of Compiler Techniques for Embedded Processors||p. 13|
|Two Emerging Approaches: Model-based and Rule-driven||p. 47|
|Practical Issues in Compiler Design for Embedded Processors||p. 67|
|Compiler Transformations for DSP Address Calculation||p. 83|
|Pushing the Capabilities of Compiler Methodologies in Industry||p. 103|
|Tools for Instruction-Set Design and Redesign||p. 125|
|Glossary of Abbreviations||p. 151|
|Table of Contents provided by Blackwell. All Rights Reserved.|
Number Of Pages: 155
Published: 30th June 1997
Country of Publication: NL
Dimensions (cm): 23.4 x 15.6 x 1.91
Weight (kg): 0.98