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Rapid Prototyping of Digital Systems : A Tutorial Approach - James O. Hamblen

Rapid Prototyping of Digital Systems

A Tutorial Approach

Paperback Published: 30th June 2004
ISBN: 9780792374398
Number Of Pages: 270

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Rapid Prototyping of Digital Systems, Second Edition provides an exciting and challenging laboratory component for an undergraduate digital logic design class. The more advanced topics and exercises are also appropriate for consideration at schools that have an upper level course in digital logic or programmable logic.
Design engineers working in industry will also want to consider this book for a rapid introduction to FPLD technology and logic synthesis using commercial CAD tools, especially if they have not had previous experience with the new and rapidly evolving technology.
Two tutorials on the Altera CAD tool environment, an overview of programmable logic, and a design library with several easy-to-use input and output functions were developed for this book to help the reader get started quickly. Early design examples use schematic capture and library components. VHDL is used for more complex designs after a short introduction to VHDL-based synthesis.
The second edition of the text now includes Altera's 10.1 student edition software which adds support for Windows 2000 and designs that are three times larger using the new 70,000 gate UP 1X board. All designs in the book's CD-Rom have been updated to work with the original UP 1 board or the newer UP 1X board using the new Altera student version software. A coupon is included with the text for purchase of the new UP 1X board. The additional logic and memory in the UP 1X's FLEX 10K70 is useful on larger design projects such as computers and video games.
In addition to the new software, the second edition includes an update chapter on programmable logic, new robot sensors and projects, optional Verilog examples, and a meta assembler which can be used to develop assemble language programs for the computer designs in Chapters 8 and 13.

Tutorial I: The 15 Minute Designp. 2
Design Entry using the Graphic Editorp. 6
Compiling the Designp. 9
Simulation of the Designp. 10
Downloading Your Design to the UP 1 or UP 1X Boardp. 12
The 10 Minute VHDL Entry Tutorialp. 14
Compiling the VHDL Designp. 17
The 10 Minute Verilog Entry Tutorialp. 17
Compiling the Verilog Designp. 21
Timing Analysisp. 22
The Floorplan Editorp. 23
Symbols and Hierarchyp. 24
Functional Simulationp. 24
For additional informationp. 25
Laboratory Exercisesp. 25
The Altera UP 1 and UP 1X CPLD Boardsp. 30
Programming Jumpersp. 31
MAX 7000 Device and UP 1 I/O Featuresp. 31
MAX and FLEX Seven-segment LED Displaysp. 31
FLEX 10K Device and UP 1 I/O Featuresp. 34
Obtaining a UP 1 or UP 1X Board and Power Supplyp. 36
Programmable Logic Technologyp. 38
CPLDs and FPGAsp. 41
Altera MAX 7000S Architecture--A Product Term CPLD Devicep. 42
Altera FLEX 10K Architecture--A Look-Up Table CPLD Devicep. 43
Xilinx 4000 Architecture--A Look-Up Table FPGA Devicep. 47
Computer Aided Design Tools for Programmable Logicp. 49
Next Generation FPLD CAD toolsp. 50
Applications of FPLDsp. 50
Features of New Generation FPLDsp. 50
For additional informationp. 51
Laboratory Exercisesp. 52
Tutorial II: Sequential Design and Hierarchyp. 54
Install the Tutorial Files and UP1core Libraryp. 54
Open the tutor2 Schematicp. 54
Browse the Hierarchyp. 56
Using Buses in a Schematicp. 57
Testing the Pushbutton Counter and Displaysp. 58
Testing the Initial Design on the UP 1 Boardp. 59
Fixing the Switch Contact Bounce Problemp. 60
Testing the Modified Design on the UP 1 Boardp. 61
Laboratory Exercisesp. 61
UP1core Library Functionsp. 66
UP1core DEC_7SEG: Hex to Seven-segment Decoderp. 67
UP1core Debounce: Pushbutton Debouncep. 68
UP1core OnePulse: Pushbutton Single Pulsep. 69
UP1core Clk_Div: Clock Dividerp. 70
UP1core VGA_Sync: VGA Video Sync Generationp. 71
UP1core CHAR_ROM: Character Generation ROMp. 73
UP1core Keyboard: Read Keyboard Scan Codep. 74
UP1core Mouse: Mouse Cursorp. 75
Using VHDL for Synthesis of Digital Hardwarep. 78
VHDL Data Typesp. 78
VHDL Operatorsp. 79
VHDL Based Synthesis of Digital Hardwarep. 80
VHDL Synthesis Models of Gate Networksp. 80
VHDL Synthesis Model of a Seven-segment LED Decoderp. 81
VHDL Synthesis Model of a Multiplexerp. 83
VHDL Synthesis Model of Tri-State Outputp. 84
VHDL Synthesis Models of Flip-flops and Registersp. 84
Accidental Synthesis of Inferred Latchesp. 86
VHDL Synthesis Model of a Counterp. 86
VHDL Synthesis Model of a State Machinep. 87
VHDL Synthesis Model of an ALU with an Adder/Subtractor and a Shifterp. 89
VHDL Synthesis of Multiply and Divide Hardwarep. 90
VHDL Synthesis Models for Memoryp. 91
Hierarchy in VHDL Synthesis Modelsp. 94
Using a Testbench for Verificationp. 96
For additional informationp. 97
Laboratory Exercisesp. 97
State Machine Design: The Electric Train Controllerp. 102
The Train Control Problemp. 102
Track Power (T1, T2, T3, and T4)p. 104
Track Direction (DA1-DA0, and DB1-DB0)p. 104
Switch Direction (SW1, SW2, and SW3)p. 105
Train Sensor Input Signals (S1, S2, S3, S4, and S5)p. 105
An Example Controller Designp. 106
VHDL Based Example Controller Designp. 110
Simulation Vector file for State Machine Simulationp. 112
Running the Train Control Simulationp. 115
Running the Video Train System (After Successful Simulation)p. 116
Laboratory Exercisesp. 117
A Simple Computer Design: The [mu]P 1p. 122
Computer Programs and Instructionsp. 123
The Processor Fetch, Decode and Execute Cyclep. 124
VHDL Model of the [mu]P 1p. 131
Simulation of the [mu]P1 Computerp. 134
Laboratory Exercisesp. 135
VGA Video Display Generationp. 140
Video Display Technologyp. 140
Video Refreshp. 140
Using a CPLD for VGA Video Signal Generationp. 143
A VHDL Sync Generation Example: UP1core VGA_SYNCp. 144
Final Output Register for Video Signalsp. 146
Required Pin Assignments for Video Outputp. 146
Video Examplesp. 147
A Character Based Video Designp. 147
Character Selection and Fontsp. 148
VHDL Character Display Design Examplesp. 151
A Graphics Memory Design Examplep. 153
Video Data Compressionp. 154
Video Color Mixing using Ditheringp. 155
VHDL Graphics Display Design Examplep. 155
Laboratory Exercisesp. 157
Communications: Interfacing to the PS/2 Keyboardp. 160
PS/2 Port Connectionsp. 160
Keyboard Scan Codesp. 161
Make and Break Codesp. 161
The PS/2 Serial Data Transmission Protocolp. 161
Scan Code Set 2 for the PS/2 Keyboardp. 164
The Keyboard UP1corep. 166
A Design Example Using the Keyboard UP1corep. 169
For Additional Informationp. 170
Laboratory Exercisesp. 170
Communications: Interfacing to the PS/2 Mousep. 172
The Mouse UP1corep. 174
Mouse Initializationp. 174
Mouse Data Packet Processingp. 175
An Example Design Using the Mouse UP1corep. 176
For Additional Informationp. 176
Laboratory Exercisesp. 176
Robotics: The UP1-botp. 178
The UP1-bot Designp. 178
UP1-bot Servo Drive Motorsp. 178
Modifying the Servos to make Drive Motorsp. 179
VHDL Servo Driver Code for the UP1-botp. 180
Sensors for the UP1-botp. 182
Assembly of the UP1-bot Bodyp. 190
UP1-bot FLEX Expansion B Header Pinsp. 197
An Alternative UP 1 Robot Project Based on an R/C Carp. 198
For Additional Informationp. 203
Laboratory Exercisesp. 204
A RISC Design: Synthesis of the MIPS Processor Corep. 210
The MIPS Instruction Set and Processorp. 210
Using VHDL to Synthesize the MIPS Processor Corep. 213
The Top-Level Modulep. 214
The Control Unitp. 217
The Instruction Fetch Stagep. 219
The Decode Stagep. 222
The Execute Stagep. 224
The Data Memory Stagep. 226
Simulation of the MIPS Designp. 227
MIPS Hardware Implementation on the UP 1 or UP 1X Boardp. 228
For Additional Informationp. 229
Laboratory Exercisesp. 230
Generation of Pseudo Random Binary Sequencesp. 235
MAX+PLUS II Design and Data File Extensionsp. 237
UP 1 and UP 1X Pin Assignmentsp. 239
The Wintim Meta Assemblerp. 243
An Introduction to Verilog for VHDL usersp. 252
Glossaryp. 259
Indexp. 267
About the Accompanying CD-ROMp. 270
Table of Contents provided by Syndetics. All Rights Reserved.

ISBN: 9780792374398
ISBN-10: 0792374398
Audience: General
Format: Paperback
Language: English
Number Of Pages: 270
Published: 30th June 2004
Country of Publication: US
Dimensions (cm): 25.5 x 17.76  x 1.55
Weight (kg): 0.51
Edition Number: 2
Edition Type: Revised