Principles of VLSI System Planning : A Framework for Conceptual Design

1 Introduction.- 1.1 Benefits of VLSI System Planning.- 1.2 VLSI System Planning Overview.- 1.3 Comparisons to Previous Related Efforts.- 1.3.1 General Problem Solving Research.- 1.3.2 VLSI Design Research.- 1.3.3 DSP Synthesis Research.- 1.4 Organization of Book.- 2 Alternatives Exploration.- 2.1 Formalizing Design Knowledge.- 2.2 Hierarchy: Controlling Complexity.- 2.3 Constraints.- 2.3.1 Ordering Constraints.- 2.3.2 Consistency Constraints.- 2.4 Delaying Design Decisions.- 2.5 Backtracking: Changing Design Decisions.- 3 Design Assistance.- 3.1 Advice.- 3.1.1 Type of Design Advice.- 3.1.2 Basis of Design Advice: Discrimination Factors.- 3.1.3 Ranking of Design Advice.- 3.2 Prediction.- 3.2.1 Taxonomy of Prediction Models.- 3.2.1.1 Heuristic Models.- 3.2.1.2 Analytical Models.- 3.2.1.2.1 Probability Theory.- 3.2.1.2.2 Graph and Information Theory.- 3.2.1.3 Simulation Models.- 3.2.2 Invoking the Prediction Models.- 4 General Software Architecture.- 4.1 User Interface.- 4.2 Conventional/AI Software Integration.- 4.2.1 Rule-Based Expert System Architecture.- 4.2.2 Data-Driven and Procedure-Driven Control.- 4.3 The Knowledge Base.- 4.3.1 Blackboard Architecture.- 4.3.1.1 Advice Knowledge Sources.- 4.3.1.2 Prediction Knowledge Sources.- 4.3.2 State and Context Switching.- 4.3.3 Controlling Search Time.- 5 A DSP VLSI System Planner.- 5.1 Algorithmic and Architectural Issues.- 5.1.1 Filter Algorithms.- 5.1.1.1 Time-Domain Characterizations.- 5.1.1.2 Frequency-Domain Characterization.- 5.1.1.3 Discrimination Factors.- 5.1.2 Polynomial Approximation Techniques.- 5.1.2.1 Discrimination Factors.- 5.1.3 Filter Architectures.- 5.1.3.1 Algorithm-Specific Architectures.- 5.1.3.2 Filter Structures.- 5.1.3.2.1 Discrimination Factors.- 5.1.3.3 Pipelining.- 5.1.3.3.1 Discrimination Factors.- 5.2 Logical Level Issues.- 5.2.1 Adder Logic Designs.- 5.2.1.1 Discrimination Factors.- 5.2.2 Multiplier Logic Designs.- 5.2.2.1 Encoding Techniques.- 5.2.2.1.1 Discrimination Factors.- 5.2.2.2 Array Designs.- 5.2.2.2.1 Discrimination Factors.- 5.2.2.3 Final Adder Designs.- 5.3 Circuit and Physical Level Issues.- 5.3.1 Layout Design Styles.- 5.3.1.1 Discrimination Factors.- 5.3.2 Fabrication Technologies.- 5.3.2.1 Discrimination Factors.- 6 A DSP Prediction Methodology.- 6.1 Algorithmic Level Predictions.- 6.1.1 FIR-related Prediction Models.- 6.1.2 IIR-related Prediction Models.- 6.2 Architectural Level Predictions.- 6.3 Logical Level Predictions.- 6.3.1 Basic Full Adder.- 6.3.2 Word Size.- 6.3.3 Adder Logic Prediction Models.- 6.3.4 Multiplier Logic Predictions.- 6.4 Physical Level Predictions.- 6.5 Experimental Results.- 7 Yoda: Sample Planning Session.- 7.1 Constraints and Delaying Decisions.- 7.2 Advice and Consistency Constraints.- 7.3 Qualitative and Quantitative Advice.- 7.4 Context Switching and Subplans.- 7.5 Backtracking.- 7.6 Invoking Prediction Models.- 8 Summary.- 8.1 Future Work.- A Commercial Digital Filter ICs.- A.1 TRW.- A.2 NCR.- A.3 Harris.- A.4 Zoran.- A.5 Inmos.- A.6 Motorola.- B Software Implementation Details.- B.1 Bicorporal Architecture.- B.2 Alternatives Exploration Subsystem.- B.2.1 Representing Plans.- B.2.2 Representing Constraints.- B.3 Design Assistance Subsystem.- B.3.1 Representing Knowledge Sources.- B.4 Code Management.- Biblography.