+612 9045 4394
 
CHECKOUT
Principles of Asynchronous Circuit Design : A Systems Perspective - Jens Sparso

Principles of Asynchronous Circuit Design

A Systems Perspective

By: Jens Sparso (Editor), Stephen B. Furber (Editor)

Hardcover

Published: 31st December 2001
Ships: 7 to 10 business days
7 to 10 business days
RRP $692.99
$479.90
31%
OFF
or 4 easy payments of $119.98 with Learn more

Other Available Formats (Hide)

  • Paperback View Product Published: 29th October 2010
    $259.53

Principles of Asynchronous Circuit Design - A Systems Perspective addresses the need for an introductory text on asynchronous circuit design. Part I is an 8-chapter tutorial which addresses the most important issues for the beginner, including how to think about asynchronous systems. Part II is a 4-chapter introduction to Balsa, a freely-available synthesis system for asynchronous circuits which will enable the reader to get hands-on experience of designing high-level asynchronous systems. Part III offers a number of examples of state-of-the-art asynchronous systems to illustrate what can be built using asynchronous techniques. The examples range from a complete commercial smart card chip to complex microprocessors.
The objective in writing this book has been to enable industrial designers with a background in conventional (clocked) design to be able to understand asynchronous design sufficiently to assess what it has to offer and whether it might be advantageous in their next design task.

Prefacep. xi
Acknowledgmentsp. xiii
Forewordp. xv
Asynchronous circuit design--A tutorial
Introductionp. 3
Why consider asynchronous circuits?p. 3
Aims and backgroundp. 4
Clocking versus handshakingp. 5
Outline of Part Ip. 8
Fundamentalsp. 9
Handshake protocolsp. 9
Bundled-data protocolsp. 9
The 4-phase dual-rail protocolp. 11
The 2-phase dual-rail protocolp. 13
Other protocolsp. 13
The Muller C-element and the indication principlep. 14
The Muller pipelinep. 16
Circuit implementation stylesp. 17
4-phase bundled-datap. 18
2-phase bundled data (Micropipelines)p. 19
4-phase dual-railp. 20
Theoryp. 23
The basics of speed-independencep. 23
Classification of asynchronous circuitsp. 25
Isochronic forksp. 26
Relation to circuitsp. 26
Testp. 27
Summaryp. 28
Static data-flow structuresp. 29
Introductionp. 29
Pipelines and ringsp. 30
Building blocksp. 31
A simple examplep. 33
Simple applications of ringsp. 35
Sequential circuitsp. 35
Iterative computationsp. 35
FOR, IF, and WHILE constructsp. 36
A more complex example: GCDp. 38
Pointers to additional examplesp. 39
A low-power filter bankp. 39
An asynchronous microprocessorp. 39
A fine-grain pipelined vector multiplierp. 40
Summaryp. 40
Performancep. 41
Introductionp. 41
A qualitative view of performancep. 42
Example 1: A FIFO used as a shift registerp. 42
Example 2: A shift register with parallel loadp. 44
Quantifying performancep. 47
Latency, throughput and wavelengthp. 47
Cycle time of a ringp. 49
Example 3: Performance of a 3-stage ringp. 51
Final remarksp. 52
Dependency graph analysisp. 52
Example 4: Dependency graph for a pipelinep. 52
Example 5: Dependency graph for a 3-stage ringp. 54
Summaryp. 56
Handshake circuit implementationsp. 57
The latchp. 57
Fork, join, and mergep. 58
Function blocks--The basicsp. 60
Introductionp. 60
Transparency to handshakingp. 61
Review of ripple-carry additionp. 64
Bundled-data function blocksp. 65
Using matched delaysp. 65
Delay selectionp. 66
Dual-rail function blocksp. 67
Delay insensitive minterm synthesis (DIMS)p. 67
Null Convention Logicp. 69
Transistor-level CMOS implementationsp. 70
Martin's adderp. 71
Hybrid function blocksp. 73
MUX and DEMUXp. 75
Mutual exclusion, arbitration and metastabilityp. 77
Mutual exclusionp. 77
Arbitrationp. 79
Probability of metastabilityp. 79
Summaryp. 80
Speed-independent control circuitsp. 81
Introductionp. 81
Asynchronous sequential circuitsp. 81
Hazardsp. 82
Delay modelsp. 83
Fundamental mode and input-output modep. 83
Synthesis of fundamental mode circuitsp. 84
Signal transition graphsp. 86
Petri nets and STGsp. 86
Some frequently used STG fragmentsp. 88
The basic synthesis procedurep. 91
Example 1: a C-elementp. 92
Example 2: a circuit with choicep. 92
Example 2: Hazards in the simple gate implementationp. 94
Implementations using state-holding gatesp. 96
Introductionp. 96
Excitation regions and quiescent regionsp. 97
Example 2: Using state-holding elementsp. 98
The monotonic cover constraintp. 98
Circuit topologies using state-holding elementsp. 99
Initializationp. 101
Summary of the synthesis processp. 101
Petrify: A tool for synthesizing SI circuits from STGsp. 102
Design examples using Petrifyp. 104
Example 2 revisitedp. 104
Control circuit for a 4-phase bundled-data latchp. 106
Control circuit for a 4-phase bundled-data MUXp. 109
Summaryp. 113
Advanced 4-phase bundled-data protocols and circuitsp. 115
Channels and protocolsp. 115
Channel typesp. 115
Data-validity schemesp. 116
Discussionp. 116
Static type checkingp. 118
More advanced latch control circuitsp. 119
Summaryp. 121
High-level languages and toolsp. 123
Introductionp. 123
Concurrency and message passing in CSPp. 124
Tangram: program examplesp. 126
A 2-place shift registerp. 126
A 2-place (ripple) FIFOp. 126
GCD using while and if statementsp. 127
GCD using guarded commandsp. 128
Tangram: syntax-directed compilationp. 128
The 2-place shift registerp. 129
The 2-place FIFOp. 130
GCD using guarded repetitionp. 131
Martin's translation processp. 133
Using VHDL for asynchronous designp. 134
Introductionp. 134
VHDL versus CSP-type languagesp. 135
Channel communication and design flowp. 136
The abstract channel packagep. 138
The real channel packagep. 142
Partitioning into control and datap. 144
Summaryp. 146
The VHDL channel packagesp. 148
The abstract channel packagep. 148
The real channel packagep. 150
Balsa - An Asynchronous Hardware Synthesis System
An introduction to Balsap. 155
Overviewp. 155
Basic conceptsp. 156
Tool set and design flowp. 159
Getting startedp. 159
A single-place bufferp. 161
Two-place buffersp. 163
Parallel composition and module reusep. 164
Placing multiple structuresp. 165
Ancillary Balsa toolsp. 166
Makefile generationp. 166
Estimating area costp. 167
Viewing the handshake circuit graphp. 168
Simulationp. 168
The Balsa languagep. 173
Data typesp. 173
Data typing issuesp. 176
Control flow and commandsp. 178
Binary/unary operatorsp. 181
Program structurep. 181
Example circuitsp. 183
Selecting channelsp. 190
Building library componentsp. 193
Parameterised descriptionsp. 193
A variable width buffer definitionp. 193
Pipelines of variable width and depthp. 194
Recursive definitionsp. 195
An n-way multiplexerp. 195
A population counterp. 197
A Balsa shifterp. 200
An arbiter treep. 202
A simple DMA controllerp. 205
Global registersp. 205
Channel registersp. 206
DMA controller structurep. 207
The Balsa descriptionp. 211
Arbiter treep. 211
Transfer enginep. 212
Control unitp. 213
Large-Scale Asynchronous Designs
Descalep. 221
Introductionp. 222
VLSI programming of asynchronous circuitsp. 223
The Tangram toolsetp. 223
Handshake technologyp. 225
GCD algorithmp. 226
Opportunities for asynchronous circuitsp. 231
Contactless smartcardsp. 232
The digital circuitp. 235
The 80C51 microcontrollerp. 236
The prefetch unitp. 239
The DES coprocessorp. 241
Resultsp. 243
Testp. 245
The power supply unitp. 246
Conclusionsp. 247
An Asynchronous Viterbi Decoderp. 249
Introductionp. 249
The Viterbi decoderp. 250
Convolution encodingp. 250
Decoder principlep. 251
System parametersp. 253
System overviewp. 254
The Path Metric Unit (PMU)p. 256
Node pair design in the PMUp. 256
Branch metricsp. 259
Slot timingp. 261
Global winner identificationp. 262
The History Unit (HU)p. 264
Principle of operationp. 264
History Unit backtracep. 264
History Unit implementationp. 267
Results and design evaluationp. 269
Conclusionsp. 271
Acknowledgementp. 272
Further readingp. 272
Processorsp. 273
An introduction to the Amulet processorsp. 274
Amulet1 (1994)p. 274
Amulet2e (1996)p. 275
Amulet3i (2000)p. 275
Some other asynchronous microprocessorsp. 276
Processors as design examplesp. 278
Processor implementation techniquesp. 279
Pipelining processorsp. 279
Asynchronous pipeline architecturesp. 281
Determinism and non-determinismp. 282
Dependenciesp. 288
Exceptionsp. 297
Memory - a case studyp. 302
Sequential accessesp. 302
The Amulet3i RAMp. 303
Cachep. 307
Larger asynchronous systemsp. 310
System-on-Chip (DRACO)p. 310
Interconnectionp. 310
Balsa and the DMA controllerp. 312
Calibrated time delaysp. 313
Production testp. 314
Summaryp. 315
Epiloguep. 317
Referencesp. 319
Indexp. 333
Table of Contents provided by Syndetics. All Rights Reserved.

ISBN: 9780792376132
ISBN-10: 0792376137
Series: European Low-Power Initiative for Electronic System Design (Series).
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 337
Published: 31st December 2001
Publisher: Springer
Country of Publication: NL
Dimensions (cm): 23.5 x 15.5  x 1.91
Weight (kg): 0.64