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Power Distribution Networks with On-Chip Decoupling Capacitors - Mikhail Popovich

Power Distribution Networks with On-Chip Decoupling Capacitors

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Published: 15th November 2007
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Power Distribution Networks with On-Chip Decoupling Capacitors is dedicated to distributing power in high speed, high complexity integrated circuits with power levels exceeding tens of watts and the power supply below a volt. The book provides insight and intuition into the behavior and design of integrated circuit-based power distribution systems.

The book has three primary objectives. The first is to describe the impedance characteristics of the overall power distribution system, from the voltage regulator through the printed circuit board and package onto the integrated circuit to the power terminals of the on-chip circuitry. The second is to discuss the inductive characteristics of on-chip power distribution grids and the related circuit behavior of these structures. The third objective is to present design methodologies for effciently placing on-chip decoupling capacitors in nanoscale integrated circuits.

Power Distribution Networks with On-Chip Decoupling Capacitors is a reference for professional engineers in the fields of circuits and systems and computer-aided design.

Introductionp. 1
Evolution of integrated circuit technologyp. 3
Evolution of design objectivesp. 7
The problem of power distributionp. 10
Deleterious effects of power distribution noisep. 17
Signal delay uncertaintyp. 17
On-chip clock jitterp. 17
Noise margin degradationp. 20
Degradation of gate oxide reliabilityp. 20
Book outlinep. 20
Inductive Properties of Electric Circuitsp. 27
Definitions of inductancep. 28
Field energy definitionp. 28
Magnetic flux definitionp. 30
Partial inductancep. 35
Net inductancep. 40
Variation of inductance with frequencyp. 43
Uniform current density approximationp. 44
Inductance variation mechanismsp. 45
Simple circuit modelp. 49
Inductive behavior of circuitsp. 52
Inductive properties of on-chip interconnectp. 54
Summaryp. 58
Properties of On-Chip Inductive Current Loopsp. 59
Introductionp. 59
Dependence of inductance on line lengthp. 60
Inductive coupling between two parallel loop segmentsp. 67
Application to circuit analysisp. 68
Summaryp. 69
Electromigrationp. 71
Physical mechanism of electromigrationp. 72
Electromigration-induced mechanical stressp. 75
Steady state limit of electromigration damagep. 76
Dependence of electromigration lifetime on the line dimensionsp. 78
Statistical distribution of electromigration lifetimep. 81
Electromigration lifetime under AC currentp. 82
Electromigration in novel interconnect technologiesp. 83
Designing for electromigration reliabilityp. 85
Summaryp. 86
High Performance Power Distribution Systemsp. 87
Physical structure of a power distribution systemp. 88
Circuit model of a power distribution systemp. 89
Output impedance of a power distribution systemp. 92
A power distribution system with a decoupling capacitorp. 95
Impedance characteristicsp. 95
Limitations of a single-tier decoupling schemep. 99
Hierarchical placement of decoupling capacitancep. 101
Resonance in power distribution networksp. 108
Full impedance compensationp. 114
Case studyp. 116
Design considerationsp. 119
Inductance of the decoupling capacitorsp. 119
Interconnect inductancep. 120
Limitations of the one-dimensional circuit modelp. 121
Summaryp. 124
Decoupling Capacitancep. 125
Introduction to decoupling capacitancep. 126
Historical retrospectivep. 126
Decoupling capacitor as a reservoir of chargep. 127
Practical model of a decoupling capacitorp. 129
Impedance of power distribution system with decoupling capacitorsp. 133
Target impedance of a power distribution systemp. 133
Antiresonancep. 136
Hydraulic analogy of hierarchical placement of decoupling capacitorsp. 140
Intrinsic vs intentional on-chip decoupling capacitancep. 145
Intrinsic decoupling capacitancep. 146
Intentional decoupling capacitancep. 150
Types of on-chip decoupling capacitorsp. 152
Polysilicon-insulator-polysilicon (PIP) capacitorsp. 153
MOB capacitorsp. 155
Metal-insulator-metal (MIM) capacitorsp. 163
Lateral flux capacitorsp. 165
Comparison of on-chip decoupling capacitorsp. 169
On-chip switching voltage regulatorp. 171
Summaryp. 173
On-Chip Power Distribution Networksp. 175
Styles of on-chip power distribution networksp. 176
Basic structure of on-chip power distribution networksp. 176
Improving the impedance characteristics of on-chip power distribution networksp. 181
Evolution of power distribution networks in Alpha microprocessorsp. 182
Die-package interfacep. 184
Other considerationsp. 189
Summaryp. 191
Computer-Aided Design and Analysisp. 193
Design flow for on-chip power distribution networksp. 194
Linear analysis of power distribution networksp. 199
Modeling power distribution networksp. 201
Characterizing the power current requirements of on-chip circuitsp. 207
Numerical methods for analyzing power distribution networksp. 210
Allocation of on-chip decoupling capacitorsp. 217
Charge-based allocation methodologyp. 218
Allocation strategy based on the excessive noise amplitudep. 220
Allocation strategy based on excessive chargep. 221
Summaryp. 223
Inductive Properties of On-Chip Power Distribution Gridsp. 225
Power transmission circuitp. 225
Simulation setupp. 228
Grid typesp. 228
Inductance versus line widthp. 233
Dependence of inductance on grid typep. 234
Non-interdigitated versus interdigitated gridsp. 234
Paired versus interdigitated gridsp. 235
Dependence of Inductance on grid dimensionsp. 236
Dependence of inductance on grid widthp. 236
Dependence of inductance on grid lengthp. 238
Sheet inductance of power gridsp. 238
Efficient computation of grid inductancep. 239
Summaryp. 241
Variation of Grid Inductance with Frequencyp. 243
Analysis approachp. 243
Discussion of inductance variationp. 245
Circuit modelsp. 245
Analysis of inductance variationp. 248
Summaryp. 250
Inductance/Area/Resistance Tradeoffsp. 253
Inductance vs. resistance tradeoff under a constant grid area constraintp. 253
Inductance vs. area tradeoff under a constant grid resistance constraintp. 258
Summaryp. 260
Scaling Trends of On-Chip Power Distribution Noisep. 263
Prior workp. 264
Interconnect characteristicsp. 266
Global interconnect characteristicsp. 268
Scaling of the grid inductancep. 268
Flip-chip packaging characteristicsp. 269
Impact of on-chip capacitancep. 271
Model of power supply noisep. 272
Power supply noise scalingp. 274
Analysis of constant metal thickness scenariop. 274
Analysis of the scaled metal thickness scenariop. 275
ITRS scaling of power noisep. 277
Implications of noise scalingp. 281
Summaryp. 282
Impedance Characteristics of Multi-Layer Gridsp. 285
Electrical properties of multi-layer gridsp. 287
Impedance characteristics of individual grid layersp. 287
Impedance characteristics of multi-layer gridsp. 290
Case study of a two layer gridp. 292
Simulation setupp. 293
Inductive coupling between grid layersp. 293
Inductive characteristics of a two layer gridp. 297
Resistive characteristics of a two layer gridp. 298
Variation of impedance with frequency in a two layer gridp. 300
Design implicationsp. 301
Summaryp. 302
Multiple On-Chip Power Supply Systemsp. 305
ICs with multiple power supply voltagesp. 306
Multiple power supply voltage techniquesp. 307
Clustered voltage scaling (CVS)p. 309
Extended clustered voltage scaling (ECVS)p. 310
Challenges in ICs with multiple power supply voltagesp. 311
Die areap. 312
Power dissipationp. 312
Design complexityp. 313
Placement and routingp. 313
Optimum number and magnitude of available power supply voltagesp. 316
Summaryp. 321
On-Chip Power Distribution Grids with Multiple Supply Voltagesp. 323
Backgroundp. 325
Simulation setupp. 325
Power distribution grid with dual supply and dual groundp. 328
Interdigitated grids with DSDGp. 331
Type I interdigitated grids with DSDGp. 331
Type II interdigitated grids with DSDGp. 333
Paired grids with DSDGp. 335
Type I paired grids with DSDGp. 336
Type II paired grids with DSDGp. 337
Simulation resultsp. 340
Interdigitated power distribution grids without decoupling capacitorsp. 341
Paired power distribution grids without decoupling capacitorsp. 348
Power distribution grids with decoupling capacitorsp. 349
Dependence of power noise on the switching frequency of the current loadsp. 353
Design implicationsp. 356
Summaryp. 358
Decoupling Capacitors for Multi-Voltage Power Distribution Systemsp. 361
Impedance of a power distribution systemp. 363
Impedance of a power distribution systemp. 364
Antiresonance of parallel capacitorsp. 367
Dependence of impedance on power distribution system parametersp. 368
Case study of the impedance of a power distribution systemp. 371
Voltage transfer function of power distribution systemp. 376
Voltage transfer function of a power distribution systemp. 376
Dependence of voltage transfer function on power distribution system parametersp. 378
Case study of the voltage response of a power distribution systemp. 381
Overshoot-free magnitude of a voltage transfer functionp. 383
Tradeoff between the magnitude and frequency rangep. 385
Summaryp. 389
On-chip Power Noise Reduction Techniques in High Performance ICsp. 391
Ground noise reduction through an additional low noise on-chip groundp. 393
Dependence of ground bounce reduction on system parametersp. 395
Physical separation between noisy and noise sensitive circuitsp. 396
Frequency and capacitance variationsp. 397
Impedance of an additional ground pathp. 399
Summaryp. 400
Effective Radii of On-Chip Decoupling Capacitorsp. 403
Backgroundp. 405
Effective radius of on-chip decoupling capacitor based on a target impedancep. 407
Estimation of required on-chip decoupling capacitancep. 409
Dominant resistive noisep. 410
Dominant inductive noisep. 411
Critical line lengthp. 414
Effective radius as determined by charge timep. 416
Design methodology for placing on-chip decoupling capacitorsp. 422
Model of on-chip power distribution networkp. 422
Case studyp. 425
Design implicationsp. 431
Summaryp. 432
Efficient Placement of Distributed On-Chip Decoupling Capacitorsp. 435
Technology constraintsp. 436
Placing on-chip decoupling capacitors in nanoscale ICsp. 437
Design of a distributed on-chip decoupling capacitor networkp. 440
Design tradeoffs in a distributed on-chip decoupling capacitor networkp. 445
Dependence of system parameters on R[subscript 1]p. 446
Minimum C[subscript 1]p. 447
Minimum total budgeted on-chip decoupling capacitancep. 448
Design methodology for a system of distributed on-chip decoupling capacitorsp. 450
Case studyp. 453
Summaryp. 457
Impedance/Noise Issues in On-Chip, Power Distribution Networksp. 459
Scaling effects in chip-package resonancep. 460
Propagation of power distribution noisep. 463
Local inductive behaviorp. 465
Summaryp. 469
Conclusionsp. 471
Appendices
Mutual Loop Inductance in Fully Interdigitated Power Distribution Grids with DSDGp. 477
Mutual Loop Inductance in Pseudo-Interdigitated Power Distribution Grids with DSDGp. 479
Mutual Loop Inductance in Fully Paired Power Distribution Grids with DSDGp. 481
Mutual Loop Inductance in Pseudo-Paired Power Distribution Grids with DSDGp. 483
Referencesp. 485
Indexp. 509
Table of Contents provided by Ingram. All Rights Reserved.

ISBN: 9780387716008
ISBN-10: 0387716009
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 516
Published: 15th November 2007
Publisher: Springer-Verlag New York Inc.
Country of Publication: US
Dimensions (cm): 23.5 x 15.5  x 3.18
Weight (kg): 2.07