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Power Distribution Networks in High Speed Integrated Circuits - Andrey Mezhiba

Power Distribution Networks in High Speed Integrated Circuits

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Published: 1st November 2003
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Distributing power in high speed, high complexity integrated circuits has become a challenging task as power levels exceeding tens of watts have become commonplace while the power supply is plunging toward one volt. This book is dedicated to this important subject. The primary purpose of this monograph is to provide insight and intuition into the behavior and design of power distribution systems for high speed, high complexity integrated circuits. The impedance characteristics of the overall power distribution system, from voltage regulator through the printed circuit board and package onto the integrated circuit to the power terminals of the on-chip circuitry, are described. The design and analysis of the hierarchy of decoupling capacitors used to improve the impedance characteristics are presented. The inductive characteristics of on-chip power distribution grids are described and the effect of these characteristics on circuit behaviour is discussed. Techniques and algorithms for the computer-aided design and analysis of on-chip power distribution networks are also described; The emphasis of the book is on developing circuit intuition and understanding the principles that govern the design and operation of power distribution systems.

From the reviews: "This authoritative and interesting book concentrates on explanation of behavior and design of power distribution systems for high-speed and high-complex ICs. ... It is a nice introductory text on basic principles that govern the design and operation of on-chip power distribution networks. This book is timely, and very well written. Its style is clear and readable. It should make an important reference book ! . an excellent work and should be read by many of us. It is ! an instructive and informative well-written book." (Mile Stojcev, Microelectronics Reliability, Vol. 44, 2004)

List of Figuresp. xiii
List of Tablesp. xix
Prefacep. xxi
Introductionp. 1
Evolution of integrated circuit technologyp. 2
Evolution of design objectivesp. 5
The problem of power distributionp. 8
Deleterious effects of power distribution noisep. 13
Signal delay uncertaintyp. 13
On-chip clock jitterp. 13
Noise margin degradationp. 15
Degradation of gate oxide reliabilityp. 16
Book outlinep. 16
Inductive Properties of Electric Circuitsp. 21
Definitions of inductancep. 22
Field energy definitionp. 22
Magnetic flux definitionp. 24
Partial inductancep. 29
Net inductancep. 34
Variation of inductance with frequencyp. 37
Uniform current density approximationp. 37
Inductance variation mechanismsp. 38
Simple circuit modelp. 42
Inductive behavior of circuitsp. 44
Inductive properties of on-chip interconnectp. 47
Summaryp. 50
Properties of On-chip Inductive Current Loopsp. 53
Introductionp. 53
Dependence of inductance on line lengthp. 54
Inductive coupling between two parallel loop segmentsp. 60
Application to circuit analysisp. 62
Summaryp. 63
Electromigrationp. 65
Physical mechanism of electromigrationp. 66
Electromigration-induced mechanical stressp. 69
Steady state limit of electromigration damagep. 69
Dependence of electromigration lifetime on the line dimensionsp. 71
Statistical distribution of electromigration lifetimep. 74
Electromigration lifetime under AC currentp. 75
Electromigration in novel interconnect technologiesp. 76
Designing for electromigration reliabilityp. 78
Summaryp. 79
High Performance Power Distribution Systemsp. 81
Physical structure of a power distribution systemp. 82
Circuit model of a power distribution systemp. 83
Output impedance of a power distribution systemp. 86
A power distribution system with a decoupling capacitorp. 89
Impedance characteristicsp. 89
Limitations of a single-tier decoupling schemep. 92
Hierarchical placement of decoupling capacitancep. 94
Resonance in power distribution networksp. 100
Full impedance compensationp. 107
Case studyp. 109
Design considerationsp. 111
Inductance of the decoupling capacitorsp. 112
Interconnect inductancep. 113
Limitations of the one-dimensional circuit modelp. 114
Summaryp. 116
On-chip Power Distribution Networksp. 119
Styles of on-chip power distribution networksp. 120
Basic structure of on-chip power distribution networksp. 120
Improving the impedance characteristics of on-chip power distribution networksp. 125
Evolution of power distribution networks in Alpha microprocessorsp. 126
Allocation of on-chip decoupling capacitancep. 128
Types of on-chip decoupling capacitancep. 128
Allocation strategiesp. 132
On-chip switching voltage regulatorp. 136
Die-package interfacep. 138
Other considerationsp. 143
Summaryp. 144
Computer-Aided Design and Analysisp. 147
Design flow for on-chip power distribution networksp. 148
Linear analysis of power distribution networksp. 153
Modeling power distribution networksp. 154
Characterizing the power current requirements of on-chip circuitsp. 160
Numerical methods for analyzing power distribution networksp. 163
Summaryp. 169
Inductive Properties of On-chip Power Distribution Gridsp. 171
Power transmission circuitp. 171
Simulation setupp. 174
Grid typesp. 174
Inductance versus line widthp. 176
Dependence of inductance on grid typep. 180
Non-interdigitated versus interdigitated gridsp. 180
Paired versus interdigitated gridsp. 181
Dependence of Inductance on grid dimensionsp. 181
Dependence of inductance on grid widthp. 182
Dependence of inductance on grid lengthp. 183
Sheet inductance of power gridsp. 184
Efficient computation of grid inductancep. 184
Summaryp. 186
Variation of Grid Inductance With Frequencyp. 187
Analysis approachp. 187
Discussion of inductance variationp. 189
Circuit modelsp. 189
Analysis of inductance variationp. 192
Summaryp. 194
Inductance/Area/Resistance Tradeoffsp. 197
Inductance vs. resistance tradeoff under a constant grid area constraintp. 197
Inductance vs. area tradeoff under a constant grid resistance constraintp. 201
Summaryp. 204
Scaling Trends of On-chip Power Distribution Noisep. 205
Prior workp. 206
Interconnect characteristicsp. 209
Global interconnect characteristicsp. 209
Scaling of the grid inductancep. 210
Flip-chip packaging characteristicsp. 211
Impact of on-chip capacitancep. 212
Model of power supply noisep. 214
Power supply noise scalingp. 215
Analysis of constant metal thickness scenariop. 215
Analysis of the scaled metal thickness scenariop. 217
ITRS scaling of power noisep. 218
Implications of noise scalingp. 222
Summaryp. 223
Impedance Characteristics of Multi-layer Gridsp. 225
Electrical properties of multi-layer gridsp. 227
Impedance characteristics of individual grid layersp. 227
Impedance characteristics of multi-layer gridsp. 229
Case study of a two layer gridp. 232
Simulation setupp. 232
Inductive coupling between grid layersp. 233
Inductive characteristics of a two layer gridp. 236
Resistive characteristics of a two layer gridp. 237
Variation of impedance with frequency in a two layer gridp. 239
Design implicationsp. 240
Summaryp. 241
Inductive Effects in On-chip Power Distribution Networksp. 243
Scaling effects in chip-package resonancep. 244
Propagation of power distribution noisep. 246
Local inductive behaviorp. 248
Summaryp. 252
Conclusionsp. 255
Referencesp. 259
Indexp. 275
About the Authorsp. 279
Table of Contents provided by Ingram. All Rights Reserved.

ISBN: 9781402075346
ISBN-10: 1402075340
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 280
Published: 1st November 2003
Publisher: Springer-Verlag New York Inc.
Country of Publication: US
Dimensions (cm): 23.5 x 15.5  x 2.54
Weight (kg): 1.34