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Nanometer Technology Designs : High-Quality Delay Tests - Nisar Ahmed

Nanometer Technology Designs

High-Quality Delay Tests

Hardcover Published: 1st November 2007
ISBN: 9780387764863
Number Of Pages: 281

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Adopting new fabrication technologies not only provides higher integration and enhances performance, but also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz timing-related defects havv become a high proportion of the total chip defects. For nanometer technology designs, the stuck-at fault test alone cannot ensure a high quality level of chips. At-speed tests using the transition fault model has become a requirement in technologies below 180nm.

Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise (including IR-drop, ground bounce, and Ldi/dt) effects on chip performance, high test pattern volume, low fault/defect coverage, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.

Introductionp. 1
Introduction to VLSI Testingp. 1
Defectsp. 3
Fault Modelsp. 4
Types of Defectsp. 6
Types of Testingp. 8
Classification Based of Paradigm of Testingp. 8
Classification Based on Measurement Parametersp. 11
Voltage-Based Testingp. 12
Current-Based Testingp. 14
System-on-Chip (SoC)p. 15
SoC Testingp. 15
SoC Test is Expensivep. 15
SoC Tester: An Examplep. 16
Design For Testability (DFT)p. 17
DFT Techniquesp. 18
Built-In Self-Test (BIST)p. 18
Scan or Full Scanp. 19
Boundary Scan (BS)p. 21
Delay Fault Testingp. 22
Path-Delay Faultsp. 23
Transition Delay Faultsp. 24
Referencesp. 26
At-speed Test Challenges for Nanometer Technology Designsp. 29
Technology Scaling Effectsp. 29
Crosstalk Effectsp. 31
Power Supply Noise Effectsp. 32
Process Variations Effectsp. 35
Thermal Effectsp. 36
Statistical Analysisp. 37
High Quality Test Patternsp. 37
Small Delay Defectsp. 38
Using Low-Cost Testers to Reduce Capital Test Costp. 39
Local At-Speed Scan Enable Generationp. 40
At-Speed I/O Testingp. 40
Referencesp. 40
Local At-Speed Scan Enable Generation Using Low-Cost Testersp. 45
Introductionp. 46
A Big Picture of Low-cost Testersp. 49
Background and Motivationp. 50
Local Scan Enable Signal Generationp. 54
Last Transition Generator (LTG)p. 55
Operation of LTG Cellp. 57
DFT Architecturep. 59
Multiple Clock Domain Analysisp. 63
LTG Insertion Flowp. 64
ATPGp. 65
Experimental Resultsp. 67
Summaryp. 70
Referencesp. 71
Enhanced Launch-Off-Capturep. 73
Introductionp. 74
Overview of Enhanced LOC Methodp. 77
Enhanced Launch-off-Capturep. 78
Local Scan Enable Signal (LSEN) Generationp. 82
Local Scan Enable Generator (LSEG)p. 83
Operation of LSEG Cellp. 85
Scan Insertion and ATPG Flowp. 85
Test Architecturep. 85
Test Synthesis and ATPGp. 87
Case Studyp. 89
Analysis of ELOC Detected Additional Faultsp. 91
Experimental Resultsp. 94
Summaryp. 97
Referencesp. 98
Hybrid Scan-Based Transition Delay Testp. 101
Introductionp. 102
Overview of the Hybrid Methodp. 103
Motivationp. 103
Local Scan Enable Signal (LSEN) Generationp. 106
Local Scan Enable Generator (LSEG) Cellsp. 106
Slow Scan Enable Generator (SSEG)p. 106
Fast Scan Enable Generator (FSEG)p. 107
Operation of LSEG cellsp. 108
Flip-Flop Selection: ATPG-Based Controllability/Observability Measurementp. 108
CASE Study: DFT Insertion, ATPG Flow and Fault Analysisp. 110
Test Architecturep. 110
Case Studyp. 111
DFT Insertion Based on Controllability/Observability Measurep. 112
ATPGp. 114
Analysis of Extra Detected Faultsp. 115
Experimental Resultsp. 116
Summaryp. 118
Referencesp. 118
Avoiding Functionally Untestable Faultsp. 121
Introductionp. 121
Overview of the Frameworkp. 123
Functionally Untestable Fault Identificationp. 125
Constraint Generation, Minimization, and Realizationp. 127
Constraint Generationp. 128
Constraint Minimizationp. 128
Constraint Realizationp. 129
Framework Implementationp. 130
Analysisp. 131
Summaryp. 133
Referencesp. 133
Screening Small Delay Defectsp. 135
Introductionp. 136
Overview of the Proposed Timing-based Pattern Generation Procedurep. 139
Path Length and Pattern Delay Analysisp. 140
Endpoint Definitionp. 142
Pattern Generationp. 142
Pattern Selectionp. 145
Experimental Resultsp. 147
Pre-processing Phasep. 147
Pattern Generation and Selection Phasep. 149
Summaryp. 152
Referencesp. 154
Faster-Than-At-Speed Test Considering IR-drop Effectsp. 157
Introductionp. 158
Overview of the Faster-Than-At-Speed Test Techniquep. 160
Case Study: Design Implementationp. 160
Test Pattern Delay Analysisp. 162
Dynamic IR-drop Analysis at Functional Speedp. 164
Dynamic IR-drop Analysis at Faster-than-at-speed Testp. 166
Pattern Generation Frameworkp. 168
Pattern Groupingp. 168
Estimation of Performance Degradationp. 169
Experimental Resultsp. 173
Summaryp. 174
Referencesp. 174
IR-drop Tolerant At-speed Test Pattern Generationp. 177
Introductionp. 177
Overview of the IR-drop Tolerant Pattern Generation Methodp. 179
Case Study 1: ITC'99 Benchmark b19p. 179
Physical Design Implementationp. 180
Statistical IR-drop Analysisp. 181
Dynamic IR-drop Analysisp. 182
Average Power Modelp. 185
Pattern Generation Frameworkp. 186
Experimental Resultsp. 190
Case Study 2: Cadence SOC Design 'Turbo-Eagle'p. 190
Test Strategy using Statistical IR-drop Analysisp. 193
Switching Cycle Average Power (SCAP) Modelp. 196
Fault List Manipulation and Pattern Generationp. 197
Experimental Resultsp. 198
Summaryp. 204
Referencesp. 204
Pattern Generation for Power Supply Noise Analysisp. 207
Introductionp. 207
Overview of the Methodp. 209
Power Supply Noise (PSN) Modelp. 209
Pattern Generationp. 212
Timing of Switching Eventsp. 212
Preprocessing Phasep. 215
Algorithmp. 215
Pseudocodep. 216
Examplep. 216
Experimental Resultsp. 219
Summaryp. 220
Referencesp. 220
Delay Fault Testing in Presence of Maximum Crosstalkp. 223
Technology Scaling Effect on Crosstalkp. 223
Overview of the Methodp. 227
Preliminary Analysis: Proximity and Transition Directionp. 227
Victim/Aggressor Proximityp. 228
Victim/Aggressor Transition Directionp. 228
Inducing Coupling Effects on Critical Pathsp. 229
Path Segmentation and Couplingp. 229
Inducing Coupling Effectsp. 231
Pattern Generation Flow with Neighboring Crosstalk Sensitizationp. 232
Parasitic Extractionp. 233
Critical Path Identification and Segmentationp. 234
Test Pattern Generationp. 235
Experimental Results and Analysisp. 235
Summaryp. 238
Referencesp. 239
Testing SoC Interconnects for Signal Integrityp. 241
Introductionp. 241
Technology Scaling Effects on Signal Integrityp. 241
Overviewp. 243
Overviewp. 247
Testing Interconnects Using Multiple Transition (MT) Fault Modelp. 247
Enhanced Boundary Scan Cellsp. 252
Test Architecturep. 259
Implementation and Simulation Resultsp. 264
Testing Interconnects Using MA Modelp. 268
Test Data Compressionp. 269
EX-SITEST Instruction and Test Processp. 271
Resultsp. 271
Summaryp. 273
Referencesp. 273
Indexp. 277
Table of Contents provided by Ingram. All Rights Reserved.

ISBN: 9780387764863
ISBN-10: 0387764860
Series: Frontiers in Electronic Testing
Audience: Tertiary; University or College
Format: Hardcover
Language: English
Number Of Pages: 281
Published: 1st November 2007
Publisher: Springer-Verlag New York Inc.
Country of Publication: US
Dimensions (cm): 23.5 x 15.5  x 1.91
Weight (kg): 0.62