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Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits - Piet Wambacq

Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits

By: Piet Wambacq (Editor), Georges Gielen (Editor), John Gerrits (Editor)

Hardcover Published: 31st July 2001
ISBN: 9780792374329
Number Of Pages: 294

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Modern system-on-chip designs are increasingly mixed-signal designs that require efficient systematic design methodologies and supporting computer-aided design (CAD) tools to manage the design complexity in the available design time, that is ever decreasing due to tightening time-to-market constraints. The purpose of this work is to provide an overview of research results that have been achieved as part of the Low-Power Initiative of the European Union, in the field of analog, RF and mixed-signal design methodologies and CAD tools. It is a representative sampling of the state-of-the art in this area, with special focus on low-power design methodologies and tools for analog and RF circuits and architectures. Concrete designs, mainly for telecommunication applications, such as low-noise amplifiers, oscillators, filters, but also complete transceiver front-ends, are discussed and analyzed in a methodological way, and their modeling and simulation, both at the circuit level and at the architectural level, are treated. In this way, the eleven contributions of this book combine in a unique way designs with methodologies and CAD that should be interesting to designers and CAD developers, both in industry and academia.

List of Figuresp. xi
List of Tablesp. xix
Contributing Authorsp. xxi
Forewordp. xxv
Introductionp. xxxi
Motivation, context and objectivesp. 1
Analysis and simulation of RF subsystemsp. 9
Steady-state analysisp. 9
Harmonic Balance and Shootingp. 10
Fast Methodsp. 12
Multitime analysisp. 14
Autonomous Systems: the Warped MPDEp. 18
Macromodelling time-varying systemsp. 22
Noise in RF designp. 25
Mixing noisep. 27
Phase Noisep. 32
Conclusionsp. 36
Referencesp. 40
FAST: an efficient high-level dataflow simulator of mixed-signal front-ends of digital telecom transceiversp. 43
High-level models of front-end blocksp. 46
Multirate multicarrier (MRMC) representation of signalsp. 47
Computation of the response to an MRMC signalp. 49
Combinatorial approachp. 49
Fourier transform approachp. 50
Construction of a computational graphp. 50
Scheduling and executionp. 51
Coupling of FAST with the digital simulation environment OCAPIp. 52
Runtime examplesp. 53
Influence of the buffer size on the CPU timep. 53
Processing of nonlinear blocksp. 54
Conclusionsp. 57
Referencesp. 58
Efficient high-level simulation of analog telecom frontendsp. 61
Situating the exponential approach within a global framework for simulation algorithmsp. 62
Basic ideas behind simulationp. 63
An overview of some existing simulation algorithmsp. 65
The complex damped exponential approachp. 67
The complex damped exponential basis and its signal modeling capabilitiesp. 67
A simulation approach using complex damped exponentialsp. 70
Elementary arithmetics using exponentialsp. 70
Algorithms for dealing with linear systemsp. 70
Algorithms for dealing with weakly nonlinear systemsp. 72
Conversion between sampled data and exponential representationp. 74
Experimental resultsp. 75
Conclusionsp. 79
Referencesp. 80
High-level power estimation of analog front-end blocksp. 83
System design of telecom front endsp. 83
Localising the digital and the analog partp. 84
Refining the analog partp. 85
Conclusions from current system design and possible improvementsp. 86
Analog power estimatorsp. 87
High-level power estimationp. 87
Construction of power estimatorsp. 89
First approach: bottom-upp. 89
Second approach: top-downp. 91
Illustration of both approachesp. 92
Conclusionsp. 93
Examples of fundamental relations used to estimate the power consumptionp. 93
Analog integrated continuous-time filteringp. 93
Analog signal processing: mixersp. 94
Conclusions on fundamental estimatorsp. 95
Practical high-level power estimatorsp. 95
A power estimation model for high-speed CMOS ADCsp. 95
Power estimation using neural networksp. 98
High-level power estimation of analog continuous-time filtersp. 99
Conclusion about practical estimatorsp. 103
Summaryp. 103
Referencesp. 104
Models and Analysis Techniques for Systematic Design and Verification of Frequency Synthesizersp. 107
Aspects of modelingp. 108
Why modeling?p. 108
Modeling requirementsp. 109
Introduction to frequency synthesizersp. 109
A typical frequency synthesizer topologyp. 110
The design trade-offp. 111
Phase noise evaluationp. 112
Identification and quantification of noise sourcesp. 112
Propagation from the noise source to the output nodep. 113
Combination of all contributionsp. 114
Numerical aspectsp. 115
Behavioral models for top-down designp. 116
Synthesizer models for transceiver functional-level designp. 118
Top-down behavioral-level models for synthesizer designp. 119
Illustration: settling time evaluation during top-down designp. 121
Behavioral models for bottom-up verificationp. 122
Accurate nonlinear model of the local oscillatorp. 123
Illustration: phase noise evaluation of a complete frequency synthesizer at the verification stagep. 125
Summaryp. 128
Referencesp. 128
Nonlinear Symbolic Network Analysis: Algorithms and Applications to RF Circuitsp. 131
Algorithmp. 132
Terminologyp. 132
Description of the algorithm fundamentalsp. 133
Nonlinearity stamps for 2nd- and 3rd-order analysisp. 137
Implementation of the algorithmp. 139
Error control algorithmp. 141
Error tolerancesp. 142
Applications of nonlinear symbolic analysisp. 143
Two-stage miller-compensated opampp. 143
Downconverting mixerp. 149
Conclusionsp. 151
Referencesp. 151
Approaches to Formal Verification of Analog Circuitsp. 155
Formal Verification: The Alternative Approachp. 155
Design Flowp. 156
Circuit Descriptionp. 157
Circuit Classesp. 158
Other Approachesp. 159
Linear Dynamic Systemsp. 160
Linear Circuit Descriptionp. 160
Basic Algorithmp. 160
Outer Enclosurep. 160
Inner Enclosurep. 162
Safe Path Between Two Pointsp. 162
Inner Enclosure of a Value Set Using Curvature Examinationp. 164
Extended Algorithm Including Frequency Intervalp. 165
Example: gmC-Filterp. 166
Circuit Descriptionp. 166
Experimental Resultsp. 168
Nonlinear Static Systems under Parameter Tolerancesp. 168
Algorithmp. 168
Outer Enclosurep. 169
Start Intervalsp. 171
Solution Space Deviationp. 172
Inner Enclosurep. 173
Example: Differential Pairp. 173
Nonlinear Dynamic Systems with Nominal Parametersp. 176
State Space Descriptionp. 177
Algorithmp. 177
Nonlinear Mapping of State Space Descriptionsp. 177
Sampling the State Spacep. 179
Obtaining the Linear Mapping Matricesp. 182
Adjustment of the Operating Pointp. 184
Step Size Controlp. 184
Transient Error Stimuli Generationp. 185
Example: Log-Domain-Filterp. 186
Verification Resultsp. 187
Conclusionsp. 189
Referencesp. 189
A Low Power BiCMOS 1 GHz Super-Regenerative Transceiver for ISM Applicationsp. 193
Explanation of the approach followedp. 194
Basic principles of super-regenerationp. 195
Selection of the oscillator circuitp. 198
LC oscillatorp. 198
Inductor choicep. 200
Oscillator operating modesp. 200
Receiver performance optimizationp. 201
Adjustment of the oscillator tail currentp. 202
Improved harmonic oscillator circuitp. 202
Overall receiver architecturep. 203
Receiver isolation amplifier and oscillator schematicsp. 204
Transmitter architecturep. 206
Transmitter Power Amplifier schematicsp. 206
The Sampled Phase-Locked Loopp. 207
The complete Transceiver circuit and its performancep. 209
Measurement resultsp. 209
Receiver sensitivityp. 209
Receiver selectivityp. 210
Performance summaryp. 211
Conclusionp. 212
Referencesp. 212
Low-Voltage Switched-Capacitor Filtersp. 215
Standard structures for low-voltage SC circuitsp. 219
Improved solutions for low-voltage SC circuitsp. 223
On-chip supply voltage multiplierp. 225
On-chip clock voltage multiplierp. 226
Switched-opamp techniquesp. 227
Circuit level considerationsp. 231
Opamp designp. 231
Common-mode feedback (CMFB) designp. 236
Reduction of charge loss due to voltage spikesp. 238
A SOA SC filter design examplep. 239
Open issues and future developmentsp. 244
Active switched-opamp series switchp. 244
Opamp supply voltage reductionp. 245
Conclusionsp. 248
Referencesp. 249
CMOS Low-Noise Amplifier Designp. 251
LNA Input Matchingp. 252
Reflection Coefficientp. 252
Scattering parametersp. 253
Typical LNA Input Matching Networksp. 255
LNA Noise optimizationp. 258
The P-N MOS Input Stage with Inductive Degenerationp. 259
The Variable Gain Amplifierp. 261
Variable Gain Implementationp. 261
The complete LNAp. 261
Output Bufferp. 263
Measurement Resultsp. 263
Conclusionsp. 265
Referencesp. 265
Practical Harmonic Oscillator Designp. 267
Introductionp. 267
The harmonic oscillatorp. 268
Second order resonator configurationsp. 270
Resonator tappingp. 274
Two-port resonatorsp. 276
Practical design examplesp. 277
Oscillator in bipolar technology using off-chip resonatorp. 278
Oscillator in CMOS technology using on-chip resonatorp. 282
Conclusionsp. 289
Referencesp. 290
Indexp. 291
Table of Contents provided by Syndetics. All Rights Reserved.

ISBN: 9780792374329
ISBN-10: 0792374320
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 294
Published: 31st July 2001
Publisher: SPRINGER VERLAG GMBH
Country of Publication: NL
Dimensions (cm): 23.42 x 17.88  x 1.98
Weight (kg): 0.71