Lecture Notes in Computer Science

13th International Conference, CAV 2001, Paris, France, July 18-22, 2001. Proceedings

By: Gerard Berry (Editor), Hubert Comon (Editor), Alain Finkel (Editor)

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Paperback | 4 July 2001

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This volume contains the proceedings of the conference on Computer-Aided Veric ation (CAV 2001),held in Paris, Palaisde laMutualit e, July 18{22,2001. CAV 2001 was the 13th in a series of conferences dedicated to the advan- ment of the theory and practice of computer-assisted formal analysis methods for software and hardware systems. The CAV conference covers the spectrum from theoretical results to concrete applications, with an emphasis on practical veri cation tools and algorithms and techniques needed for their implemen- tion. ProgramCommitteeofCAV 2001 Rajeev Alur (Penn. &Bell labs) Bengt Jonsson (Uppsala) Henrik Reif Andersen (Copenhagen) Robert Kurshan (LucentBellLabs) G erard Berry (EsterelT. ,co-chair) Kim G. Larsen (Aalborg) Randy Bryant (CMU) Ken Mc Millan(Cadence) Jerry Burch (Cadence) Kedar Namjoshi (Belllabs) Ching-Tsun Chou (Intel) Christine Paulin-Mohring (Orsay) Edmund Clarke (CMU) Carl Pixley (Motorola) Hubert Comon (LSV& Stanford, co-chair) Kavita Ravi (Cadence) David Dill (Stanford) Natarajan Shankar (SRI) E. Allen Emerson (Austin) Mary Sheeran (Chalmers &Prover T. ) Alain Finkel (LSV,co-chair) Tom Shiple (Synopsys) Patrice Godefroid (Belllabs) A.

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You Can Find This Book In

Non-Fiction Medicine Medicine in General Computing & I.T.Computer Science Computer Architecture & Logic Design Databases Data Capture & Analysis Systems Analysis & Design Mathematics Mathematical Foundation Mathematical Logic

Artificial Intelligence Expert Systems & Knowledge-Based Systems Computer Programming & Software Development Software Engineering

Software Documentation and the Verification Process
Certifying Model Checkers
Formalizing a JVML Verifier for Initialization in a Theorem Prover
Automated Inductive Verification of Parameterized Protocols
Efficient Model Checking via Buchi Tableau Automata
Fast LTL to Buchi Automata Translation
A Practical Approach to Coverage in Model Checking
A Fast Bisimulation Algorithm
Symmetry and Reduced Symmetry in Model Checking
Transformation-Based Verification Using Generalized Retiming
Meta-BDDs: A Decomposed Representation for Layered Symbolic Manipulation of Boolean Functions
CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination
Finite Instantiations in Equivalence Logic with Uninterpreted Functions
Model-Checking with Formula-Dependent Abstract Models
Verifying Network Protocol Implementations by Symbolic Refinement Checking
Automatic Abstraction for Verification of Timed Circuits and Systems
Automated Verification of a Randomized Distributed Concensus Protocol Using Cadence SMV and PRISM
Analysis of Recursive State Machines
Parameterized Verification with Automatically Computed Inductive Assertions
EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations
AGVI - Automatic Generation, Verification, and Implementation of Security Protocols
ICS: Integrated Canonizer and Solver
[mu]CLR: A Toolset for Analysing Algebraic Specifications
Truth/SLC - A Parallel Verification Platform for Concurrent Systems
The SLAM Toolkit
Java Bytecode Verification: An Overview
Iterating Transducers
Attacking Symbolic State Explosion
A Unifying Model Checking Approach for Safety Properties of Parameterized Systems
A BDD-Based Model Checker for Recursive Programs
Model Checking the World Wide Web
Distributed Symbolic Model Checking for [mu]-Calculus
The Temporal Logic Sugar
TREX: A Tool for Reachability Analysis of Complex Systems
BOOSTER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction
SDLcheck: A Model Checking Tool
EASN: Integrating ASN.1 and Model Checking
RTDT: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams
TAXYS: A Tool for the Development and Verification of Real-Time Embedded Systems
Microarchitecture Verification by Compositional Model Checking
Rewriting for Symbolic Execution of State Machine Models
Using Timestamping and History Variables to Verify Sequential Consistency
Benefits of Bounded Model Checking at an Industrial Setting
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2[superscript m])
Job-Shop Scheduling Using Timed Automata
As Cheap as Possible Efficient Cost-Optimal Reachability for Priced Timed Automata
Binary Reachability Analysis of Pushdown Timed Automata with Dense Clocks
Author Index
Table of Contents provided by Blackwell. All Rights Reserved.

Lecture Notes in Computer Science

13th International Conference, CAV 2001, Paris, France, July 18-22, 2001. Proceedings

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