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IDDQ Testing of VLSI Circuits : Frontiers in Electronic Testing - Ravi K. Gulati

IDDQ Testing of VLSI Circuits

Frontiers in Electronic Testing

By: Ravi K. Gulati (Editor), Charles F. Hawkins (Editor)

Hardcover

Published: 31st December 1992
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Power supply current monitoring to detect CMOS IC defects during production testing quietly laid down its roots in the mid-1970s. Both Sandia Labs and RCA in the United States and Philips Labs in the Netherlands practiced this procedure on their CMOS ICs. At that time, this practice stemmed simply from an intuitive sense that CMOS ICs showing abnormal quiescent power supply current (IDDQ) contained defects. Later, this intuition was supported by data and analysis in the 1980s by Levi (RACD, Malaiya and Su (SUNY-Binghamton), Soden and Hawkins (Sandia Labs and the University of New Mexico), Jacomino and co-workers (Laboratoire d'Automatique de Grenoble), and Maly and co-workers (Carnegie Mellon University). Interest in IDDQ testing has advanced beyond the data reported in the 1980s and is now focused on applications and evaluations involving larger volumes of ICs that improve quality beyond what can be achieved by previous conventional means. In the conventional style of testing one attempts to propagate the logic states of the suspended nodes to primary outputs. This is done for all or most nodes of the circuit. For sequential circuits, in particular, the complexity of finding suitable tests is very high. In comparison, the IDDQ test does not observe the logic states, but measures the integrated current that leaks through all gates. In other words, it is like measuring a patient's temperature to determine the state of health. Despite perceived advantages, during the years that followed its initial announcements, skepticism about the practicality of IDDQ testing prevailed. The idea, however, provided a great opportunity to researchers. New results on test generation, fault simulation, design for testability, built-in self-test, and diagnosis for this style of testing have since been reported. After a decade of research, we are definitely closer to practice.

Forewordp. 1
Prefacep. 3
I[subscript DDQ] Testing: A Reviewp. 5
I[subscript DDQ] Testing as a Component of a Test Suite: The Need for Several Fault Coverage Metricsp. 19
I[subscript DDQ] Testing in CMOS Digital ASICsp. 31
Reliability Benefits of I[subscript DDQ]p. 41
Quiescent Current Analysis and Experimentation of Defective CMOS Circuitsp. 51
QUIETEST: A Methodology for Selecting I[subscript DDQ] Test Vectorsp. 63
Generation and Evaluation of Current and Logic Tests for Switch-Level Sequential Circuitsp. 73
Diagnosis of Leakage Faults with I[subscript DDQ]p. 81
Algorithms for I[subscript DDQ] Measurement Based Diagnosis of Bridging Faultsp. 91
Proportional BIC Sensor for Current Testingp. 101
Design of ICs Applying Built-In Current Testingp. 111
Indexp. 121
Table of Contents provided by Blackwell. All Rights Reserved.

ISBN: 9780792393153
ISBN-10: 0792393155
Series: Frontiers in Electronic Testing
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 124
Published: 31st December 1992
Publisher: Springer
Country of Publication: NL
Dimensions (cm): 27.31 x 20.32  x 1.91
Weight (kg): 0.5