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High-Level Synthesis for Real-Time Digital Signal Processing : The Springer International Series in Engineering and Computer Science - Jan Vanhoof

High-Level Synthesis for Real-Time Digital Signal Processing

The Springer International Series in Engineering and Computer Science

Hardcover Published: 31st January 1993
ISBN: 9780792393139
Number Of Pages: 302

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High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler.
The emergence of independent silicon foundries, the reduced price of silicon real estate and the shortened processing turn-around time bring silicon technology within reach of system houses. Even for low volumes, digital systems on application-specific integrated circuits (ASICs) are becoming an economically meaningful alternative for traditional boards with analogue and digital commodity chips.
ASICs cover the application region where inefficiencies inherent to general-purpose components cannot be tolerated. However, full-custom handcrafted ASIC design is often not affordable in this competitive market. Long design times, a high development cost for a low production volume, the lack of silicon designers and the lack of suited design facilities are inherent difficulties to manual full-custom chip design.
To overcome these drawbacks, complex systems have to be integrated in ASICs much faster and without losing too much efficiency in silicon area and operation speed compared to handcrafted chips. The gap between system design and silicon design can only be bridged by new design (CAD). The idea of a silicon compiler, translating a behavioural system specification directly into silicon, was born from the awareness that the ability to fabricate chips is indeed outrunning the ability to design them. At this moment, CAD is one order of magnitude behind schedule. Conceptual CAD is the keyword to mastering the design complexity in ASIC design and the topic of this book.

Introductionp. 1
History and related workp. 2
Design methodologies for silicon compilationp. 7
Design methodologies for architecture synthesisp. 8
The CATHEDRAL silicon compilersp. 9
Outline of this bookp. 10
DSP architecture synthesisp. 11
Digital signal processingp. 12
DSP system specificationsp. 15
DSP target architecturesp. 26
Building a DSP silicon compilerp. 35
Implementation of data structuresp. 59
Literature surveyp. 59
Memory management strategyp. 60
Constrained storagep. 73
Unconstrained storagep. 88
Selecting resource types and instancesp. 90
Organising indirectly-addressed memoriesp. 93
Organising directly-addressed memoriesp. 100
Physical address generationp. 109
Implementation of high-level operationsp. 116
Code expansion strategyp. 116
Explicitising data dependenciesp. 122
Code expansionp. 125
Data routingp. 140
Implementation of control functionsp. 147
Literature surveyp. 147
Control function implementation strategyp. 149
Selectionp. 152
Repetitionp. 166
Hierarchyp. 170
Multi-rate systemsp. 170
Schedulingp. 180
Scheduling strategyp. 180
Scheduling algorithmsp. 187
Graph transformationsp. 209
The balancerp. 218
Estimatorsp. 223
Structure generationp. 233
Literature surveyp. 233
Structure generation strategyp. 236
Instance assignmentp. 237
Netlist generationp. 241
Execution unit parametersp. 250
Demonstrator designsp. 256
An 8-ary baseband PAM modem for ISDNp. 257
An 800 bit/s voice coderp. 273
Bibliographyp. 283
Indexp. 298
Table of Contents provided by Blackwell. All Rights Reserved.

ISBN: 9780792393139
ISBN-10: 0792393139
Series: The Springer International Series in Engineering and Computer Science
Audience: General
Format: Hardcover
Language: English
Number Of Pages: 302
Published: 31st January 1993
Publisher: Springer
Country of Publication: NL
Dimensions (cm): 23.4 x 15.6  x 2.54
Weight (kg): 1.36