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High-Level Power Analysis and Optimization - Anand Raghunathan

High-Level Power Analysis and Optimization

Hardcover Published: 30th November 1997
ISBN: 9780792380733
Number Of Pages: 175

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High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level.
High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power.
High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.

List of Figures
List of Tables
Introductionp. 1
Low power designp. 2
Design abstraction and levels of the design hierarchyp. 5
Benefits of high-level power analysis and optimizationp. 12
Book overviewp. 15
Backgroundp. 17
Sources of power consumptionp. 18
Methods for reducing power and energy consumptionp. 22
High-level design techniquesp. 25
High-level synthesis application domainsp. 33
Architecture-Level Power Estimationp. 37
Analytical power modelsp. 38
Characterization based activity and power macromodelsp. 43
Power and switching activity estimation techniques for control logicp. 67
Conclusionsp. 78
Power Managementp. 81
Clock-based power management: Gated and multiple clocksp. 82
Pre-computationp. 93
Scheduling to enable power managementp. 95
Operand isolationp. 97
Power management through constrained register sharingp. 102
Controller-based power managementp. 107
Conclusionsp. 114
High-Level Synthesis for Low Powerp. 115
Behavioral transformationsp. 116
Module selectionp. 126
Resource sharingp. 129
Schedulingp. 135
Supply voltage vs. switched capacitance trade-offsp. 139
Optimizing memory power consumption during high-level synthesisp. 142
Reducing glitching power consumption during high-level designp. 145
Conclusionsp. 153
Conclusions and Future Workp. 155
Referencesp. 159
Indexp. 173
Table of Contents provided by Blackwell. All Rights Reserved.

ISBN: 9780792380733
ISBN-10: 0792380738
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 175
Published: 30th November 1997
Publisher: Springer
Country of Publication: NL
Dimensions (cm): 25.4 x 17.8  x 1.91
Weight (kg): 1.33