+612 9045 4394
 
CHECKOUT
$7.95 Delivery per order to Australia and New Zealand
100% Australian owned
Over a hundred thousand in-stock titles ready to ship
Field-Programmable Logic : Architectures, Synthesis and Applications : 4th International Workshop on Field-Programmable Logic and Applications, Fpl'94 :  Architectures, Synthesis and Applications : 4th International Workshop on Field-Programmable Logic and Applications, Fpl'94 - Reiner W. Hartenstein

Field-Programmable Logic : Architectures, Synthesis and Applications : 4th International Workshop on Field-Programmable Logic and Applications, Fpl'94

Architectures, Synthesis and Applications : 4th International Workshop on Field-Programmable Logic and Applications, Fpl'94

By: Reiner W. Hartenstein (Editor), Michal Z. Servit (Editor)

Paperback Published: September 1994
ISBN: 9783540584193
Number Of Pages: 439

Share This Book:

Paperback

$147.02
or 4 easy payments of $36.76 with Learn more
Ships in 15 business days

Earn 294 Qantas Points
on this Book

This volume contains the proceedings of the 4th International Workshop on Field-Programmable Logic and Applications (FPL '94), held in Prague, Czech Republic in September 1994. The growing importance of field-programmable devices is substantiated by the remarkably high number of 116 submissions for FPL '94; from them, the revised versions of 40 full papers and 24 high-quality poster presentations were accepted for inclusion in this volume. Among the topics treated are: testing, layout, synthesis tools, compilation research and CAD, trade-offs and experience, innovations and smart applications, FPGA-based computer architectures, high-level design, prototyping and ASIC emulators, commercial devices, new tools, CCMs and HW/SW co-design, modelers, educational experience, and novel architectures.

Fault Modeling and Test Generation for FPGAsp. 1
A Test Methodology Applied to Cellular Logic Programmable Gate Arraysp. 11
Integrated Layout Synthesis for FPGAsp. 23
Influence of Logic Block Layout Architecture on FPGA Performancep. 34
A Global Routing Heuristic for FPGAs Based on Mean Field Annealingp. 45
Power Dissipation Driven FPGA Place and Route Under Delay Constraintsp. 57
FPGA Technology Mapping for Power Minimizationp. 66
Specification and Synthesis of Complex Arithmetic Operators for FPGAsp. 78
A Speed-Up Technique for Synchronous Circuits Realized as LUT-Based FPGAsp. 89
An Efficient Technique for Mapping RTL Structures onto FPGAsp. 99
A Testbench Design Method Suitable for FPGA-Based Prototyping of Reactive Systemsp. 111
Using Consensusless Covers for Fast Operating on Boolean Functionsp. 114
Formal Verification of Timing Rules in Design Specificationsp. 117
Optimized Synthesis of Self-Testable Finite State Machines (FSM) Using BIST-PST Structures in Altera Structuresp. 120
A High-Speed Rotation Processorp. 123
The MD5 Message-Digest Algorithm in the XILINX FPGAp. 126
A Reprogrammable Processor for Fractal Image Compressionp. 129
Implementing GCD Systolic Arrays on FPGAp. 132
Formal CAD Techniques for Safety-Critical FPGA Design and Deployment in Embedded Subsystemsp. 135
Direct Sequence Spread Spectrum Digital Radio DSP Prototyping Using Xilinx FPGAsp. 138
FPGA Based Reconfigurable Architecture for a Compact Vision Systemp. 141
A New FPGA Architecture for Word-Oriented Datapathsp. 144
Image Processing on a Custom Computing Platformp. 156
A Superscalar and Reconfigurable Processorp. 168
A Fast FPGA Implementation of a General Purpose Neuronp. 175
Data-Procedural Languages for FPL-Based Machinesp. 183
Implementing On Line Arithmetic on PAMp. 196
Software Environment for WASMII: a Data Driven Machine with a Virtual Hardwarep. 208
Constraint-Based Hierarchical Placement of Parallel Programsp. 220
ZAREPTA: A Zero Lead-Time, All Reconfigurable System for Emulation, Prototyping and Testing of ASICsp. 230
Simulating Static and Dynamic Faults in BIST Structures with a FPGA Based Emulatorp. 240
FPGA Based Prototyping for Verification and Evaluation in Hardware-Software Cosynthesisp. 251
FPGA Based Low Cost Generic Reusable Module for the Rapid Prototyping of Subsystemsp. 259
FPGA Development Tools: Keeping Pace with Design Complexityp. 271
Meaningful Benchmarks for Logic Optimization of Table-Lookup FPGAsp. 274
Educational Use of Field Programmable Gate Arraysp. 277
HardWire: A Risk-Free FPGA-to-ASIC Migration Pathp. 280
Reconfigurable Hardware from Programmable Logic Devicesp. 283
On some Limits of XILINX Based Control Logic Implementationsp. 286
Experiences of Using XBLOX for Implementing a Digital Filter Algorithmp. 289
Continuous Interconnect provides solution to Density/Performance Trade-Off in Programmable Logicp. 292
A High Density Complex PLD Family optimized for Flexibility, Predictability and 100% Routabilityp. 295
Design Experience with Fine-Grained FPGAsp. 298
FPGA Routing Structures from Real Circuitsp. 303
A Tool-Set for Simulating Altera-PLDs Using VHDLp. 306
A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modulesp. 309
Performance Characteristics of the Monte-Carlo Clustering Processor (MCCP) - a Field Programmable Logic Based Custom Computing Machinep. 312
A Design Environment with Emulation of Prototypes for Hardware/Software Systems Using XILINX FPGAp. 315
DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniquesp. 318
The Architecture of a General-Purpose Processor Cellp. 321
The Design of a Stack-Based Microprocessorp. 326
Implementation and Performance Evaluation of an Image Pre-Processing Chain on FPGAp. 332
Signature Testability of PLAp. 335
A FPL Prototyping Package with a C++ Interface for the PC Busp. 338
Design of Safety Systems Using Field Programmable Gate Arraysp. 341
A Job Dispatcher-Collector Made of FPGAs for a Centralized Voice Serverp. 344
An Optoelectronic 3-D Field Programmable Gate Arrayp. 352
On Channel Architecture and Routability for FPGAs Under Faulty Conditionsp. 361
High-Performance Datapath Implementation on Field-Programmable Multi-Chip Module (FPMCM)p. 373
A Laboratory for a Digital Design Course Using FPGAsp. 385
COordinate Rotation Digital Computer (CORDIC) Synthesis for FPGAp. 397
MARC: A Macintosh NUBUS-Expansion Board Based Reconfigurable Test System for Validating Communication Systemsp. 409
Artificial Neural Network Implementation on a Fine-Grained FPGAp. 421
Author Indexp. 433
Table of Contents provided by Blackwell. All Rights Reserved.

ISBN: 9783540584193
ISBN-10: 3540584196
Series: Lecture Notes in Computer Science
Audience: General
Format: Paperback
Language: English
Number Of Pages: 439
Published: September 1994
Publisher: SPRINGER VERLAG GMBH
Country of Publication: DE
Dimensions (cm): 23.39 x 15.6  x 2.34
Weight (kg): 0.64

Earn 294 Qantas Points
on this Book