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Field-Programmable Logic and Applications : 11th International Conference, Fpl 2001, Belfast, Northern Ireland, Uk, August 27-29, 2001 Proceedings - Gordon Brebner

Field-Programmable Logic and Applications

11th International Conference, Fpl 2001, Belfast, Northern Ireland, Uk, August 27-29, 2001 Proceedings

By: Gordon Brebner (Editor), Roger Woods (Editor)


Published: 15th August 2001
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This book contains all of the papers presented at the 11th International C- ference on Field Programmable Logic and Applications (FPL 2001), hosted by The Queen's University of Belfast, Northern Ireland,27-29 August 2001. The annual FPL event is the longest-standing international conference covering p- grammable logic, recon?gurable computing, and related matters. It was founded in 1991, and has been held in Darmstadt, Glasgow, London, Oxford (thrice), Prague, Tallinn, Vienna, and Villach. FPL brings together experts, users, and newcomers from industry and academia, in an informal and convivial atmosphere that encourages stimulating and productive interaction between participants. The size of the FPL conference has been growing rapidly, the number of participants increasing from 144 in 1999 to 240 in 2000. The number of papers submitted in 2001 was in line with the previous year, and our goal for 2001 was to sustain the growth in participation. The 117 submitted papers came from 24 di?erent countries: USA (26), UK (24), Germany (14), Spain (12), Japan (7), France (4), Greece and Ireland (3 each), Belgium, Canada, Czech Republic, Finland, Italy, The Netherlands, Poland, and Switzerland (2 each), and Austria, Belarus, Brazil, Iran, Mexico, Portugal, South Africa, and Sweden (1 each). This illustrates the position of FPL as a genuinely international event, with by far the largest number of submissions of any conference in this ?eld. As in previous years, each submitted paper was subjected to thorough reviewing. As a result, 56 regular papers and 15 posters were accepted for presentation. Another three keynote papers were invited. We thank all the authors who submitted papers, and also thank the members of the program committee and the additional referees who carefully reviewed the submissions.

Technology Trends and Adaptive Computingp. 1
Prototyping Framework for Reconfigurable Processorsp. 6
An Emulator for Exploring RaPiD Configurable Computing Architecturesp. 17
A New Placement Method for Direct Mapping into LUT-Based FPGAsp. 27
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuitsp. 37
Macrocell Architectures for Product Term Embedded Memory Arraysp. 48
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAsp. 59
Memory Synthesis for FPGA-Based Reconfigurable Computersp. 70
Implementing a Hidden Markov Model Speech Recognition System in Programmable Logicp. 81
Implementation (Normalised) RLS Lattice on Virtexp. 91
Accelerating Matrix Product on Reconfigurable Hardware for Signal Processingp. 101
Static Profile-Driven Compilation for FPGAsp. 112
Synthesizing RTL Hardware from Java Byte Codesp. 123
PuMA++: From Behavioral Specification to Multi-FPGA-Prototypep. 133
Secure Configuration of Field Programmable Gate Arraysp. 142
Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithmp. 152
JBits Implementations of the Advanced Encryption Standard (Rijndael)p. 162
Task-Parallel Programming of Reconfigurable Systemsp. 172
Chip-Based Reconfigurable Task Managementp. 182
Configuration Caching and Swappingp. 192
Multiple Stereo Matching Using an Extended Architecturep. 203
Implementation of a NURBS to Bezier Conversor with Constant Latencyp. 213
Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systemsp. 223
Processing Models for the Next Generation Networkp. 232
Tightly Integrated Placement and Routing for FPGAsp. 233
Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arraysp. 243
Reconfigurable Router Modules Using Network Protocol Wrappersp. 254
Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardwarep. 264
The MOLEN [rho][mu]-Coded Processorp. 275
Run-Time Optimized Reconfiguration Using Instruction Forecastingp. 286
CRISP: A Template for Reconfigurable Instruction Set Processorsp. 296
Evaluation of an FPGA Implementation of the Discrete Element Methodp. 306
Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solversp. 315
A Reconfigurable Embedded Input Device for Kinetically Challenged Personsp. 326
Bubble Partitioning for LUT-Based Sequential Circuitsp. 336
Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBitsp. 346
Placing, Routing, and Editing Virtual FPGAsp. 357
Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiverp. 367
A Music Synthesizer for FPGAp. 377
Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocodersp. 388
Loop Tiling for Reconfigurable Acceleratorsp. 398
The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systemsp. 409
A n-Bit Reconfigurable Scalar Quantiserp. 420
Real Time Morphological Image Contrast Enhancement in Virtex FPGAp. 430
Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processingp. 441
Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardwarep. 451
The Evolution of Programmable Logic: Past, Present, and Future Predictionsp. 461
Dynamically Reconfigurable Coresp. 462
Reconfigurable Breakpoints for Co-debugp. 473
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verificationp. 483
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuitsp. 493
A Generic Library for Adaptive Computing Environmentsp. 503
Generative Development System for FPGA Processors with Active Componentsp. 513
Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machinesp. 523
System Level Tools for DSP in FPGAsp. 534
Parameterized Function Evaluation for FPGAsp. 544
Efficient Constant Coefficient Multiplication Using Advanced FPGA Architecturesp. 555
A Digit-Serial Structure for Reconfigurable Multipliersp. 565
FPGA Resource Reduction Through Truncated Multiplicationp. 574
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architecturesp. 584
An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammarsp. 590
Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approachp. 595
An Approach to Real-Time Visualization of PIV Method with FPGAp. 601
FPGA-Based Discrete Wavelet Transforms Systemp. 607
X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressorp. 613
Arithmetic Operation Oriented Reconfigurable Chip: RHWp. 618
Initial Analysis of the Proteus Architecturep. 623
Building Asynchronous Circuits with JBitsp. 628
Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linuxp. 633
A Reconfigurable Approach to Packet Filteringp. 638
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Codingp. 643
A Data Re-use Based Compiler Optimization for FPGAsp. 648
Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardwarep. 653
A System on Chip for Power Line Communications According to European Home Systems Specificationsp. 658
Author Indexp. 663
Table of Contents provided by Blackwell. All Rights Reserved.

ISBN: 9783540424994
ISBN-10: 3540424997
Series: Lecture Notes in Computer Science,
Audience: General
Format: Paperback
Language: English
Number Of Pages: 665
Published: 15th August 2001
Country of Publication: DE
Dimensions (cm): 23.39 x 15.6  x 3.51
Weight (kg): 0.95