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Digital Hardware Testing : Transistor-level Fault Modeling and Testing - Rochit Rajsuman

Digital Hardware Testing

Transistor-level Fault Modeling and Testing

Hardcover

Published: 19th December 1992
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Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits. The discussion details design-for-testability and built-in self-test methods, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path.

Prefacep. xiii
Introduction to Digital IC Testingp. 1
Introductionp. 1
Testing Problem and Considerationsp. 2
Computational Complexity of Testing Problemp. 3
Estimation of Difficulty in Controllability and Observabilityp. 4
Summaryp. 8
Problemsp. 8
p. 8
Faults in Digital Circuitsp. 9
Introductionp. 9
General VLSI Fault Modelsp. 10
Stuck-at Fault Modelp. 10
Bridging and Open Fault Modelp. 11
Fault Equivalence, Dominance, and Collapsingp. 13
Parametric and Transient Faultsp. 14
Delay Fault Modelsp. 14
Specific Fault Modelsp. 15
PLA Fault Modelp. 15
Memory Fault Modelp. 16
Microprocessor Fault Modelp. 17
Summaryp. 18
Problemsp. 18
Referencesp. 19
Bridging Faults in Random Logicp. 21
Introductionp. 21
Characterization of Bridging Faultsp. 21
Bridging within a Logic Elementp. 22
Bridging of Logical Nodes without Feedbackp. 25
Bridging of Logical Nodes with Feedbackp. 33
Bridging in Dynamic Gatesp. 37
CMOS Domino Logicp. 38
Cascade Voltage Switch Logicp. 40
Clocked CMOS Logicp. 40
Effect of Substrate Connectionp. 42
Summaryp. 49
Problemsp. 50
Referencesp. 51
Open Faults in Random Logicp. 53
Introductionp. 53
Modeling of Open Faultsp. 53
Problems in Testing Open Faultsp. 55
Test Invalidation by Timing Skewsp. 55
Test Invalidation by Charge Distributionp. 57
Test Invalidation Due to Glitchesp. 57
Methods to Test Stuck-Open Faultsp. 59
Robust Test Sequencesp. 59
Testable Designsp. 60
Testability of Dynamic Circuitsp. 67
Summaryp. 68
Problemsp. 68
Referencesp. 69
Test Generation and Fault Simulationp. 71
Introductionp. 71
Test Generation at Gate Levelp. 71
Boolean Difference Methodp. 72
Path Sensitization and D-Algorithmp. 75
Algorithm PODEMp. 78
Algorithm FANp. 79
Fault Coverage by a Testp. 82
Critical Path Tracingp. 83
Multiple Faultsp. 87
Random Test Generationp. 89
Test Generation at Switch Levelp. 93
Fault Simulationp. 96
Summaryp. 98
Problemsp. 99
Referencesp. 99
Testing of Structured Designs (PLAs)p. 101
Introductionp. 101
Structure of a PLAp. 101
Easily Testable PLAp. 105
PLA Testing with Parity Treesp. 105
Universal Test Set for Easily Testable PLAsp. 106
Variations of Parity-Based Testable Designp. 109
Built-in Self-Test PLAp. 111
Testing of EEPLAp. 111
Testing for Multiple Faults in PLAp. 116
Fault Isolation and Reconfigurationp. 119
Summaryp. 120
Problemsp. 122
Referencesp. 122
Testing of Random Access Memoryp. 123
Introductionp. 123
Test Algorithmsp. 123
Algorithm GALPATp. 124
Checker Pattern Testp. 124
Galloping Diagonal/Row/Column Testp. 125
Marching 1/0 Test Algorithmp. 126
Modified Marching 1/0 Testp. 126
Comparison and Modification for Word-Oriented Memoryp. 127
Testable Designsp. 129
BIST Memoryp. 130
Memory Partitioning Methodsp. 131
STD Architecturep. 134
Fault Diagnosis and Reconfigurationp. 138
Advantages and Disadvantagesp. 139
Summaryp. 142
Problemsp. 142
Referencesp. 143
Testing of Sequential Circuitsp. 145
Introductionp. 145
Testing Problem in Sequential Circuitsp. 145
State Table Approachp. 146
Initialization of Sequential Circuitsp. 146
State Table Verificationp. 151
Gate Level Test Generation Methodsp. 152
Sequential Test Generation by Boolean Differencep. 153
Iterative Logic Array Modelp. 155
Simulation-Based Test Generationp. 164
Divide and Conquerp. 166
Synthesis for Testabilityp. 170
Summaryp. 171
Problemsp. 172
Referencesp. 173
Microprocessor Testingp. 175
Introductionp. 175
Microprocessor Description and Testingp. 175
Instruction Set Verificationp. 176
Machine-Level Verificationp. 176
Microinstruction-Level Verificationp. 182
Bit-Sliced Microprocessorsp. 186
Testing of One-Bit Slicep. 187
Testing of k-Bit Processorp. 189
Concurrent Checkingp. 191
Error-Detecting Codesp. 192
Check-Point Techniquep. 192
Watchdog Processorp. 194
Summaryp. 194
Referencesp. 195
Design for Testabilityp. 197
Introductionp. 197
SCAN Designp. 197
Multiplexed Data Scan Designp. 198
Level Sensitive Scan Designp. 200
Pros and Consp. 203
Partial SCANp. 204
Boundary SCANp. 207
Basic Conceptp. 207
Test Access Portp. 209
Cross-Check Designp. 212
Built-in Self-Testp. 216
Test Pattern Generatorsp. 217
Deterministic Test Pattern Generatorsp. 217
Pseudorandom Test Vectorsp. 217
Pseudoexhaustivep. 222
Response Compression for BISTp. 223
Parity Testingp. 224
One-Count Testingp. 224
Syndrome Testingp. 225
Transition Countp. 226
Signature Analysisp. 227
BIST Test Structuresp. 232
Built-in Logic Block Observer (BILBO)p. 232
Self-Test Using MISRs and Parallel SRSGs (STUMPS)p. 233
Circular Self-Test Pathp. 234
Summaryp. 235
Problemsp. 236
Referencesp. 237
Current Testingp. 239
Introductionp. 239
Basic Conceptp. 239
Estimation of Fault-Free Currentp. 244
Current Through a Single Gatep. 244
Estimation of Current in a Circuitp. 247
Current Sensing Techniquesp. 249
External Current Sensorp. 249
Built-in Current Sensorp. 252
Test Generation for IDDQ Testingp. 254
Summaryp. 257
Problemsp. 260
Referencesp. 260
Reliability Testingp. 263
Introductionp. 263
Component Quality and Fault Coveragep. 264
Reliability and Failure Ratep. 265
Failure Mechanismsp. 269
Chip Related Failuresp. 269
Assembly Related Failuresp. 271
Operation Induced Failuresp. 273
Application Induced Failuresp. 279
Reliability Test Methodsp. 281
Accelerated Reliability Testingp. 282
Temperature Accelerationp. 285
Current Accelerationp. 287
Voltage Accelerationp. 288
Temperature-Humidity Accelerationp. 290
Vibration and Shock Accelerationp. 291
Temperature, Humidity, and Power Cyclingp. 291
Burn-inp. 292
Testing of Application Induced Failuresp. 293
Summaryp. 294
Problemsp. 294
Referencesp. 294
Appendix Ap. 297
Error Modelsp. 297
Computation of Aliasing Probabilityp. 298
Annotated Bibliographyp. 303
Indexp. 311
Table of Contents provided by Syndetics. All Rights Reserved.

ISBN: 9780890065808
ISBN-10: 0890065802
Series: Materials Library S.
Audience: General
Format: Hardcover
Language: English
Number Of Pages: 340
Published: 19th December 1992
Publisher: Artech House Publishers
Country of Publication: US
Dimensions (cm): 22.9 x 15.2  x 2.2
Weight (kg): 0.67