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Design Automation for Timing-Driven Layout Synthesis : The Springer International Series in Engineering and Computer Science - Sachin S. Sapatnekar

Design Automation for Timing-Driven Layout Synthesis

The Springer International Series in Engineering and Computer Science

Hardcover

Published: 31st October 1992
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The automation of layout synthesis design under stringent timing specifications is essential for state-of-the-art VLSI circuits and systems design. Especially, the timing-driven layout synthesis with optimal placement and routing of transistors with proper sizing is most critical in view of the chip area, interconnection parasitics, circuit delay and power dissipation.
This book presents a systematic and unified view of the layout synthesis problem with a strong focus on CMOS technology. The criticality of RC parasitics in the interconnects and the optimal sizing of both p-channel and n-channel translators are illustrated for motivation. Following the motivation, the problems of modeling circuit delays and translator sizing are formulated and solved with mathematical rigor. Various delay models for CMOS circuits are discussed to account for realistic interconnection parasitics, the effect of transistor sizes, and also the input slew rates. Also many of the efficient transistor sizing algorithms are critically reviewed and the most recent transistor sizing algorithm based on convex programming techniques is introduced.
For design automation of the rigorous CMOS layout synthesis, an integrated system that employs a suite of functional modules is introduced for step-by-step illustration of the design optimization process that produces highly compact CMOS layouts that meet user-specified timing and logical netlist requirements.
Through most rigorous discussion of the essential design automation process steps and important models and algorithms this book presents a unified systems approach that can be practiced for high-performance CMOS VLSI designs.
This book serves as an excellent reference, and can be used as text in advanced courses covering VLSI design, especially for design automation of physical design.

List of Figures
Acknowledgements
Introductionp. 1
The Process of IC Designp. 2
Layout Stylesp. 4
Timing-driven Layoutp. 9
Outline of the Bookp. 11
Delay Estimationp. 13
Micromodeling - The RC Modelp. 16
Macromodelingp. 31
Worst-case Delay Estimationp. 50
Delay Calculation at the Circuit Levelp. 52
Posynomial Delay Modelingp. 60
A Case Study: iCONTRAST's Timing Analyzerp. 62
Transistor Sizing Algorithms: Existing Approachesp. 81
The TILOS Algorithmp. 85
The Method of Feasible Directions (MFD) Algorithmp. 93
Lagrangian Multiplier Approachesp. 100
Two-step Optimizationp. 106
Other Approachesp. 108
Summary of Previous Approachesp. 109
A Convex Programming Approach to Transistor Sizingp. 113
The Convex Programming Algorithmp. 116
Experimental Resultsp. 133
Global Routing Using Zero-one Integer Linear Programmingp. 141
Extracting Global Routing Informationp. 146
Global Routing Phasesp. 148
Global Routing on Medium-sized Arraysp. 173
Application to Custom Logic Layoutp. 179
Handling Very Large Circuitsp. 182
Runtime Complexityp. 185
Timing-driven CMOS Layout Synthesisp. 191
A Methodology for Designing CMOS Standard Cellsp. 193
The Metal-Metal Matrix (M[superscript 3]) Layout Style for Two-level Technologiesp. 213
iCGEN : A CMOS Layout Synthesis System for Three-level Metal Technologyp. 216
Bibliographyp. 247
Indexp. 267
Table of Contents provided by Blackwell. All Rights Reserved.

ISBN: 9780792392811
ISBN-10: 0792392817
Series: The Springer International Series in Engineering and Computer Science
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 269
Published: 31st October 1992
Publisher: Springer
Country of Publication: NL
Dimensions (cm): 23.5 x 15.5  x 2.54
Weight (kg): 1.32