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Demystifying Chipmaking - Richard Yanda

Paperback Published: 28th April 2005
ISBN: 9780750677608
Number Of Pages: 280

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This book takes the reader through the actual manufacturing process of making a typical chip, from start to finish, including a detailed discussion of each step, in plain language. The evolution of today's technology is added to the story, as seen through the eyes of the engineers who solved some of the problems. The authors are well suited to that discussion since they are three of those same engineers. They have a broad exposure to the industry and its technology that extends all the way back to Shockley Laboratories, the first semiconductor manufacturer in Silicon Valley.
The CMOS (Complementary Metal-Oxide-Semiconductor) process flow is the focus of the discussion and is covered in ten chapters. The vast majority of chips made today are fabricated using this general method. In order to ensure that all readers are comfortable with the vocabulary, the first chapter carefully and clearly introduces the science concepts found in later chapters. A chapter is devoted to pointing out the differences in other manufacturing methods, such as the gallium arsenide technology that produces chips for cell phones. In addition, a chapter describing the nature of the semiconductor industry from a business perspective is included.
"The entire process of making a chip is surprisingly easy to understand. The part of the story that defies belief is the tiny dimensions: the conducting wires and other structures on a chip are more than a hundred times thinner than a hair - and getting thinner with every new chip design."
* Included CD gives the reader a much greater comprehension of the process than a strictly print book with static illustrations provides
* Authors are actual engineers who have a broad range of exposure and experience with chip technology
* Contains a unique chapter describing the nature of the semiconductor industry from a business perspective

Industry Reviews

"...a useful guide for engineers just entering the packaging sector of the semiconductor industry or for newly vetted engineering school grads." - Ron Iscoff, Editor, Chip Scale Review "Demystifying Chipmaking...will provide an interesting overview of the IC fabrication process while familiarizing you with the terminology." - Rick Nelson, Chief Editor, Test & Measurement World

Forewordp. xi
Acknowledgmentsp. xiii
About the Authorsp. xv
What's on the CD-ROM?p. xvii
IC Fabrication Overviewp. 1
Introductionp. 3
Integrated Circuitsp. 3
The Semiconductor Industryp. 6
Support Technologiesp. 7
Crystal Growth and Wafer Preparationp. 7
Contamination Controlp. 8
Circuit Design and Mask Makingp. 10
Process Diagnostics and Metrologyp. 12
Integrated Circuit Fabricationp. 13
Layeringp. 13
Patterningp. 18
Dopingp. 21
Process Control and In-line Monitoringp. 22
Test and Assemblyp. 25
Electrical Testsp. 25
Die Separationp. 25
Die Attach and Wire Bondingp. 25
Encapsulationp. 26
Final Testp. 26
Summaryp. 27
Support Technologiesp. 29
Introductionp. 31
Contamination Controlp. 33
Why Control Contamination?p. 33
Contamination Sourcesp. 35
The Cleanroomp. 36
Crystal Growth and Wafer Preparationp. 41
Introductionp. 41
Silicon Purificationp. 42
Czochralski Silicon Growthp. 43
Shaping, Grinding, Cutting and Polishingp. 46
Final Inspection and Shippingp. 47
Circuit Designp. 49
Introductionp. 49
Product Definition and New Product Planp. 50
The Design Teamp. 53
The Design Processp. 55
Design Verification and Tapeoutp. 57
Photomask and Reticle Preparationp. 59
Introductionp. 59
Reticle Substrate Preparationp. 59
Pattern Transferp. 60
Inspection and Defect Repairp. 61
Forming Wellsp. 63
Introductionp. 65
Initial Oxidationp. 71
Photolithographyp. 79
Introductionp. 79
Coat (Spin)p. 82
Exposure (Step)p. 83
Developp. 84
After Develop Inspect (ADI)p. 85
Ion Implantationp. 87
Isolate Active Areas (Shallow Trench Isolation)p. 93
Introduction to Shallow Trench Isolationp. 95
Pad Oxide Growthp. 99
Silicon Nitride Depositionp. 101
Photolithography for Photo/Etchp. 105
Hard Mask Formation Using Plasma Etchp. 107
Hard Mask Overviewp. 107
Plasma Etch Overviewp. 109
Etch Chemistry: Silicon Dioxide and Silicon Nitridep. 114
Form Trenches in Silicon with Plasma Etchp. 119
Fill Trenches with Silicon Dioxidep. 121
Chemical Mechanical Polishing (CMP) to Remove Excess Dioxidep. 123
Wet Etch Removal of Silicon Nitride and Pad Oxidep. 127
Building the Transistorsp. 129
Introductionp. 131
Thin Film Formationp. 137
Gate Dielectric Oxidationp. 137
Polycrystalline Silicon (Poly) Depositionp. 140
Nitride Cap Depositionp. 142
Poly Gate Formationp. 143
Photoresist Patterningp. 143
Plasma Etchp. 144
Source/Drain Formationp. 147
Introductionp. 147
Shallow Implantp. 149
Spacer Formationp. 149
High-Dose Implantp. 151
Annealp. 151
Salicide Formationp. 153
Sputter Cobaltp. 155
RTP Reaction Forming Silicidep. 155
Strip Residual Cobaltp. 156
Anneal the Silicidep. 156
First Level Metallizationp. 157
Introductionp. 159
Nitride and Oxide Depositionsp. 163
Nitride Depositionp. 163
Oxide Depositionp. 164
CMP Planarizationp. 167
Photo/Etch for Contact Holesp. 169
Contact Hole Photolithographyp. 169
Contact Etchp. 170
Tungsten Plug Processp. 173
Deposit Ti/TiN Barrier/Glue Layersp. 173
Tungsten CVDp. 174
Tungsten CMPp. 176
Low-k Dielectric Processp. 177
Deposit Low-k Dielectric Filmp. 177
Trench Photolithography and Etchp. 180
Copper First Level Interconnection Processp. 183
Ta/TaN Barrier Layer Depositionp. 183
Sputter Copper (Cu)p. 185
Electroplate Copper (Cu)p. 185
Copper CMPp. 186
Multilevel Metal Interconnects and Dual Damascenep. 189
Introductionp. 191
Deposit Barrier Layer and Intermetal Dielectricp. 195
Dual Damascene Processp. 197
Introductionp. 197
Via Photo/Etchp. 198
Trench Photo/Etchp. 199
Deposit Barrier Layersp. 200
Sputter Copperp. 200
Electroplate Copperp. 200
CMP to Remove Excess Copperp. 201
Deposit SiC Barrier Layerp. 202
Build Additional Layersp. 202
Form Bonding Padsp. 203
Final Passivation Processp. 205
Deposit Final Passivationp. 205
Photo/Etch for Bonding Padsp. 205
Test and Assemblyp. 207
Introductionp. 209
Wafer and Chip Testingp. 211
In-line Parametric Testp. 211
Wafer Sort (Probe)p. 212
Final Functional Testp. 213
Assembly and Packagingp. 215
Die Separationp. 215
Die Attach and Bond Pad Connectionp. 216
Encapsulationp. 218
Science Overviewp. 219
Introductionp. 221
Atoms and Moleculesp. 223
The Atomp. 223
Moleculesp. 226
Organic Moleculesp. 227
Gasesp. 229
Facts about Gasesp. 229
Ionsp. 230
Plasmap. 230
Free Radicalsp. 231
Excited Statesp. 231
Chemistryp. 233
Introductionp. 233
Thin Film Deposition Chemistryp. 233
Plasma Etch Chemistryp. 235
Solidsp. 237
Conductors and Insulatorsp. 237
Semiconductorsp. 238
pn Junctionsp. 239
Electricity, Electric and Magnetic Fieldsp. 241
Electric Charges and Fieldsp. 241
Electric Currentp. 242
Magnetic Fieldp. 243
Plasma Etch Supplement to Chapter 4p. 245
Plasma Etcher Theoryp. 247
Plasma Etch Process Requirementsp. 249
Bibliographyp. 251
Indexp. 253
Table of Contents provided by Ingram. All Rights Reserved.

ISBN: 9780750677608
ISBN-10: 0750677600
Audience: Professional
Format: Paperback
Language: English
Number Of Pages: 280
Published: 28th April 2005
Publisher: Elsevier Science & Technology
Country of Publication: GB
Dimensions (cm): 23.5 x 19.1  x 1.68
Weight (kg): 0.68