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Comprehensive Funcional Verification : The Complete Industry Cycle - Wolfgang Roesner

Comprehensive Funcional Verification

The Complete Industry Cycle

Hardcover Published: 26th May 2005
ISBN: 9780127518039
Number Of Pages: 704

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One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals.
As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text.
A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text.
* Comprehensive overview of the complete verification cycle
* Combines industry experience with a strong emphasis on functional verification fundamentals
* Includes industry examples and real-world case studies

Very good :-)

Forewordp. ix
Prefacep. xxi
Acknowledgementsp. xxv
Introduction to Verification
Verification in the Chip Design Processp. 5
Introduction to Functional Verificationp. 5
The Verification Challengep. 8
The Challenge of State Space Explosionp. 9
The Challenge of Detecting Incorrect Behaviorp. 12
Mission and Goals of Verificationp. 14
Verification Engineer "Musts"p. 18
Cost of Verificationp. 20
Engineering Costs and the Need for an Independent Verification Teamp. 20
Design Automation Toolsp. 21
Timep. 22
Areas of Verification Beyond the Scope of this Bookp. 23
The Verification Cycle: A Structured Processp. 24
Functional Specificationp. 25
Create Verification Planp. 26
Develop Environmentp. 27
Debug HDL and Environmentp. 27
Regressionp. 28
Fabricate Hardwarep. 28
Debug Fabricated Hardware (Systems Test)p. 29
Escape Analysisp. 29
Common Verification Cycle Breakdownsp. 30
Summaryp. 31
Exercisesp. 32
Verification Flowp. 35
Verification Hierarchyp. 35
Levels of Verificationp. 36
What Level to Choose?p. 41
Strategy of Verificationp. 45
Driving Principlesp. 45
Checking Strategiesp. 50
Checking the Black Boxp. 55
Putting It All Togetherp. 59
The General Simulation Environmentp. 61
Verification Methodology Evolutionp. 62
Summaryp. 68
Exercisesp. 69
Fundamentals of Simulation Based Verificationp. 73
Basic Verification Environment: A Test Benchp. 73
Stimulus Componentp. 74
Monitorp. 80
Checkerp. 82
Scoreboardp. 83
Design Under Verificationp. 85
Observation Points: Black-Box, White-Box and Grey-Box Verificationp. 86
Black Boxp. 86
White Boxp. 87
Grey Boxp. 88
Assertion Based Verification-An Overviewp. 89
The Importance of Assertionsp. 90
Assertions Express Design Intentp. 92
Classification of Assertionsp. 94
Test Benches and Testing Strategiesp. 95
Deterministic Test Benchesp. 95
Self-Checking Test Benchesp. 97
Summaryp. 101
Exercisesp. 102
The Verification Planp. 103
The Functional Specificationp. 103
The Evolution of the Verification Planp. 104
Contents of the Verification Planp. 106
Description of Verification Levelsp. 106
Required Toolsp. 107
Risks and Dependenciesp. 108
Functions to be Verifiedp. 109
Specific Tests and Methods: Environmentp. 111
Coverage Requirementsp. 115
Test Case Scenarios: Matrixp. 116
Resource Requirementsp. 117
Schedule Detailsp. 118
Verification Example: Calc1p. 121
Design Descriptionp. 121
Creating the Verification Plan for Calc1p. 125
Deterministic Verification of Calc1p. 131
Summaryp. 136
Exercisesp. 136
Simulation Based Verification
HDLs and Simulation Enginesp. 141
Hardware Description Languagesp. 143
HDL Modeling Levelsp. 143
Verification Aspects of HDLsp. 153
Simulation Engines: Introductionp. 159
Speed versus Accuracyp. 160
Making the Right Methodology Choicesp. 162
Event-Driven Simulationp. 162
Hierarchical Model Networkp. 163
Model Evaluation Over Timep. 165
Event-Driven Control of Model Evaluationp. 167
Implementation Sketch of an Event-Driven Simulation Enginep. 172
Improving Simulation Throughputp. 178
Cycle-Based Simulationp. 182
Synchronous Designp. 183
The Cycle-Based Simulation Algorithmp. 184
Extensions to Basic Cycle-Based Simulation Enginesp. 188
Waveform Viewersp. 191
Summaryp. 196
Exercisesp. 197
Creating Environmentsp. 199
Test Bench Writing Toolsp. 200
HDL Languages as Test Bench Toolp. 201
C/C++ Librariesp. 207
High-Level Verification Languagesp. 230
Other Test Bench Toolsp. 241
Verification Coveragep. 243
Overviewp. 244
Functional Verification Test Coverage versus Manufacturing Test Coveragep. 246
Structural Coveragep. 247
Functional Coveragep. 251
Coverage Bulk Data Collection and Managementp. 254
The Right Coverage Analysis Strategyp. 255
Summaryp. 256
Exercisesp. 258
Strategies for Simulation-Based Stimulus Generationp. 259
Calc2 Overviewp. 260
Calc2 Verification Planp. 263
Calc2 and the Strategies for Stimulus Generationp. 269
Strategies for Stimulus Generationp. 270
Types of Stimulus Generationp. 270
General Algorithms for Stimulus Componentsp. 275
Applying the Four Types of Stimulus Generation to Calc2p. 277
Seeding Random Test Casesp. 294
Constraint Solving in Random Environmentsp. 297
Coverage Techniques in Random Environmentsp. 301
Making Rare Events Occurp. 303
Stimulus Generation of Deadlocks and Livelocksp. 306
Summaryp. 310
Exercisesp. 311
Strategies for Results Checking in Simulation-Based Verificationp. 313
Types of Result Checkingp. 313
On-the-Fly Checking versus End-of-Test Case Checkingp. 314
Pregenerated Test Cases versus On-the-Fly Generated Test Casesp. 321
Applying the Checking Strategies to Calc2p. 322
Debugp. 334
Debug Processp. 336
How Different Types of Test Benches Affect Debugp. 349
Summaryp. 352
Exercisesp. 353
Pervasive Function Verificationp. 355
System Reset and Bring-Upp. 356
Reset Line Initializationp. 357
Scan Initializationp. 361
Testability and Built-In Self-Testp. 363
Error and Degraded Mode Handlingp. 368
Verifying Error Detectionp. 368
Verifying Self-Healing Hardwarep. 372
Verifying Hardware Debug Assistsp. 380
Verifying Scan Ring Dumpsp. 381
Low Power Mode Verificationp. 384
Power Savings Through Disabling Functional Unitsp. 385
Power Savings Through Cycle Time Degradationp. 387
Summaryp. 389
Exercisesp. 389
Re-Use Strategies and System Simulationp. 391
Re-Use Strategiesp. 392
Guidelines for Re-Usep. 395
Horizontal Re-Usep. 403
Vertical Re-Usep. 404
Applying Re-Use to Calc2p. 405
Assertion Re-Usep. 410
System Simulationp. 412
System Test Benchp. 412
Connectivity and Interaction of Unitsp. 414
Verification Challenges in a Re-Usable IP Worldp. 418
Beyond General-Purpose Logic Simulationp. 420
Accelerationp. 421
Emulationp. 427
Hardware/Software Co-verificationp. 428
Co-simulationp. 430
Summaryp. 434
Exercisesp. 435
Formal Verification
Introduction to Formal Verificationp. 439
Foundationsp. 440
Design Correctness and Specificationsp. 441
Computational Complexityp. 443
The Myth of Linear Scaling of Simulationp. 445
Mathematical Proof Methods in Formal Verificationp. 446
Formal Boolean Equivalence Checkingp. 448
The Role of Equivalence Checking in the VLSI Design Flowp. 449
Main Elements of an Equivalence Checker Toolp. 450
Sequential and Combinational Boolean Equivalence Checkingp. 451
Core Algorithms for Combinational Equivalence Checkingp. 454
Blueprint of a Modern Equivalence Checking Toolp. 465
Functional Formal Verification-Property Checkingp. 467
Property Checking vs. Sequential Equivalence Checkingp. 468
The Myth of Complete Verification with FVp. 470
Properties for an Example Designp. 471
DUV Drivers for Formal Verificationp. 476
State Space Traversal and Temporal Logicp. 479
Functional Formal Verification Tool Flowp. 483
Summaryp. 484
Exercisesp. 485
Using Formal Verificationp. 487
Property Specification Using an HDL Libraryp. 488
The Open Verification Library (OVL)p. 489
Using OVL to Specify Propertiesp. 495
The Property Specification Language PSLp. 499
Overviewp. 500
The Boolean Layer of PSLp. 501
The Temporal Layer of PSLp. 504
The Verification Layer of PSLp. 508
The Modeling Layer of PSLp. 511
Using PSL to Specify Propertiesp. 512
Advanced PSL Topics and Caveatsp. 514
Property Checking Using Formal Verificationp. 521
Property Re-Use between Simulation and FVp. 521
Model Compliationp. 522
Formal Functional Verification Algorithmsp. 523
Solutions to Address the Problem of State Space Explosionp. 527
Semi-Formal Verificationp. 530
EDA Vendors Supplying Formal and Semi-Formal Verification Toolsp. 532
Summaryp. 532
Exercisesp. 533
Comprehensive Verification
Completing the Verification Cyclep. 539
Regressionp. 540
Regression in the Verification Flowp. 540
Regression Qualityp. 542
Regression Efficiencyp. 543
Problem Trackingp. 548
Tape-Out Readinessp. 552
Metricsp. 552
Completion Criteriap. 557
Escape Analysisp. 559
Individual Bug Analysisp. 561
Escape Examplesp. 569
Escape Analysis Trendsp. 572
Summaryp. 575
Exercisesp. 577
Advanced Verification Techniquesp. 579
Save Verification Cycles-Bootstrapping the Verification Processp. 580
Separating POR and Mainline Verificationp. 580
Bootstrapping the DUV into High-Potential Statesp. 583
Manipulating the DUV Specification Provoking States of Resource Conflictp. 585
High-Level Modeling-Conceptsp. 586
Applications of the High-Level Modelp. 587
High-Level Modeling Stylesp. 590
Coverage-Directed Generationp. 595
Summaryp. 598
Exercisesp. 599
Case Studies
Case Studiesp. 603
The Line Delete Escapep. 603
The Backgroundp. 603
The Verification Environmentsp. 605
The Escapep. 607
Branch History Tablep. 608
The Backgroundp. 608
BHT Purpose and Logic Designp. 609
BHT Verificationp. 614
Resultsp. 624
Network Processorp. 624
System Overviewp. 625
Verification Effortp. 627
Resultsp. 638
Summaryp. 639
Glossaryp. 641
Referencesp. 657
Subject Indexp. 663
Table of Contents provided by Ingram. All Rights Reserved.

ISBN: 9780127518039
ISBN-10: 0127518037
Series: Systems on Silicon
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 704
Published: 26th May 2005
Publisher: Elsevier Science & Technology
Country of Publication: US
Dimensions (cm): 23.5 x 19.1  x 3.81
Weight (kg): 1.54