| List of Abbreviations | p. xi |
| Preface | p. xv |
| ADCs: Principles, Architectures, and State of the Art | p. 1 |
| Analog-to-Digital Conversion: Fundamentals | p. 2 |
| Sampling | p. 3 |
| Quantization | p. 3 |
| Oversampling ADCs: Fundamentals | p. 7 |
| Oversampling | p. 7 |
| Noise-shaping | p. 8 |
| Basic architecture of oversampling ADCs | p. 11 |
| Performance metrics | p. 15 |
| Ideal performance | p. 17 |
| Single-Loop Architectures | p. 20 |
| 1st-order modulator | p. 20 |
| 2nd-order modulator | p. 24 |
| High-order modulators | p. 27 |
| Stability concerns | p. 27 |
| Optimized NTFs | p. 28 |
| High-order topologies | p. 31 |
| Non-linear stabilization techniques | p. 33 |
| Cascade Architectures | p. 34 |
| Multi-Bit Architectures | p. 43 |
| Influence of DAC errors | p. 45 |
| Element trimming and analog calibration | p. 46 |
| Digital correction | p. 47 |
| Dynamic element matching | p. 48 |
| Dual-quantization | p. 49 |
| Leslie-Singh architecture | p. 49 |
| Single-loop Ms | p. 50 |
| Cascade Ms | p. 50 |
| Parallel Architectures | p. 52 |
| Frequency division multiplexing | p. 53 |
| Time division multiplexing | p. 53 |
| Code division multiplexing | p. 54 |
| State of the Art in ADCs | p. 54 |
| Summary | p. 65 |
| Non-Ideal Performance of Modulators | p. 67 |
| Integrator Leakage | p. 68 |
| Leaky integrator | p. 68 |
| Single-loop modulators | p. 69 |
| 1st-order loop | p. 69 |
| 2nd-order loop | p. 70 |
| Lth-order loops | p. 71 |
| Cascade modulators | p. 72 |
| Capacitor Mismatch | p. 77 |
| Single-loop modulators | p. 77 |
| 2nd-order loop | p. 77 |
| Lth-order loops | p. 78 |
| Cascade modulators | p. 79 |
| Integrator Setting Error | p. 83 |
| Model for the transient response of SC integrators | p. 84 |
| SC integrator model | p. 84 |
| Transient during integration | p. 85 |
| Transient during sampling | p. 88 |
| Integration-sampling process | p. 91 |
| Validation of the proposed model | p. 92 |
| Comparison with experimental results | p. 92 |
| Comparison with traditional models | p. 93 |
| Effect of the amplifier finite gain-bandwidth product | p. 95 |
| Single-loop modulators | p. 97 |
| Cascade modulators | p. 97 |
| Effect of the amplifier finite slew rate | p. 99 |
| Effect of the switch finite on-resistance | p. 102 |
| Effect on an ideal integrator | p. 102 |
| Effect on the amplifier GB | p. 103 |
| Effect on the amplifier SR | p. 105 |
| Circuit Noise | p. 108 |
| Noise in track-and-holds | p. 109 |
| Track component | p. 110 |
| Sampled-and-held component | p. 110 |
| Folding-back effect | p. 111 |
| Noise in SC integrators | p. 113 |
| Switches controlled by 1 | p. 114 |
| Switches controlled by 2 | p. 115 |
| Opamp noise | p. 116 |
| Noise in the references | p. 119 |
| Total noise | p. 120 |
| Circuit noise in modulators | p. 122 |
| Fully-differential circuitry | p. 123 |
| Clock Jitter | p. 124 |
| Sources of Distortion | p. 125 |
| Distortion due to the non-linear capacitors | p. 126 |
| Distortion due to the amplifier non-linear gain | p. 130 |
| Distortion due to the switch non-linear on-resistance | p. 133 |
| Distortion due to the non-linear settling | p. 138 |
| Summary | p. 139 |
| A Wideband Modulator in 3.3-V 0.35-m CMOS | p. 141 |
| Design Methodology | p. 142 |
| Topology Selection | p. 143 |
| Switched-Capacitor Implementation | p. 151 |
| Specifications for the Building Blocks | p. 153 |
| Modulator sizing | p. 153 |
| Fast modulator sizing | p. 153 |
| Fine-tuning of blocks specs | p. 157 |
| Integrator scaling | p. 159 |
| Design of the Building Blocks | p. 160 |
| Amplifiers | p. 160 |
| Front-end amplifier | p. 162 |
| Remaining amplifiers | p. 166 |
| Comparators | p. 168 |
| Switches | p. 169 |
| Capacitors | p. 170 |
| Programmable A/D/A converter | p. 173 |
| A/D converter | p. 173 |
| D/A converter | p. 174 |
| Control circuitry | p. 175 |
| Clock phase generator | p. 176 |
| Layout and Prototyping | p. 177 |
| Experimental Results | p. 179 |
| Performance of the A/D/A converter | p. 182 |
| Influence of jitter noise | p. 182 |
| Influence of settling errors | p. 183 |
| Influence of switching noise | p. 185 |
| Performance Summary | p. 188 |
| Performance Comparison with the State of the Art | p. 189 |
| Summary | p. 192 |
| A Modulator in 2.5-V 0.25-m CMOS for ADSL/ADSL+ | p. 193 |
| Topology Selection | p. 195 |
| Switched-Capacitor Implementation | p. 198 |
| Specifications for the Building Blocks | p. 198 |
| Design of the Building Blocks | p. 205 |
| Amplifiers | p. 205 |
| Front-end amplifiers | p. 205 |
| Back-end amplifiers | p. 207 |
| Non-linearities | p. 207 |
| Comparators | p. 209 |
| Switches | p. 210 |
| Capacitors | p. 212 |
| A/D/A converter | p. 212 |
| A/D converter | p. 212 |
| D/A converter | p. 214 |
| Clock phase generator | p. 214 |
| Auxiliary blocks | p. 215 |
| Reference voltage generator | p. 215 |
| Master current generator | p. 217 |
| Anti-aliasing filter | p. 217 |
| Layout and Prototyping | p. 217 |
| Experimental Results | p. 219 |
| Performance Summary | p. 223 |
| Performance Comparison with the State of the Art | p. 225 |
| Summary | p. 228 |
| A Modulator with Programmable Signal Gain for Automotive Sensor Interfaces | p. 229 |
| Basic Design Considerations | p. 231 |
| Architecture Selection and High-Level Sizing | p. 233 |
| Modulator architecture | p. 235 |
| SC implementation | p. 235 |
| High-level sizing and building-block specifications | p. 239 |
| Design of the Building Blocks | p. 239 |
| Amplifiers | p. 239 |
| Comparators | p. 243 |
| Switches | p. 244 |
| Capacitor arrays | p. 246 |
| Auxiliary blocks | p. 246 |
| Layout and Prototyping | p. 249 |
| Experimental Results | p. 251 |
| Summary | p. 256 |
| An Expandible Family of Cascade Modulators | p. 259 |
| Topology Description | p. 259 |
| Non-Ideal Performance | p. 263 |
| Power Estimator for Cascade Modulators | p. 267 |
| Dominant Error Mechanisms | p. 267 |
| Estimation of Power Consumption | p. 269 |
| References | p. 275 |
| Index | p. 293 |
| Table of Contents provided by Ingram. All Rights Reserved. |
