Algorithmic Aspects of VLSI Layout

By: Der-Tsai Lee, Majid Sarrafzadeh

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Hardcover | 1 December 1992

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Discussing algorithmic aspects of VLSI layout, this text includes coverage of: issues in timing driven layout; LP formulation of global routeing and placement; Stockmeyer's floorplan optimization technique; the Manhattan and knock-knee routeing modes; and parallel algorithms for placement.

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Non-Fiction Computing & I.T.Computer Science Computer Architecture & Logic Design Mathematical Theory of Computation Engineering & Technology Electronics & Communications Engineering Electronics Engineering Circuits & Components Computer Programming & Software Development Software Engineering Booktopia Publisher Services

World Scientific Publishing

Issues in Timing Driven Layout	p. 1
Binary Formulations for Placement and Routing Problems	p. 25
A Survey of Parallel Algorithms for VLSI Cell Placement	p. 69
Approximate Solutions for Graph and Hypergraph Partitioning	p. 133
Integer Program Formulations of Global Routing and Placement Problems	p. 167
Circuit Partitioning Algorithms Based on Geometry Model	p. 199
The Three-Dimensional Channel Routing Problem	p. 213
On the Manhattan and Knock-Knee Routing Models	p. 245
Switch-Box Routing Under the Two-Overlap Wiring Model	p. 265
A Note on the Complexity of Stockmeyer's Floorplan Optimization Technique	p. 309
An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI Floorplan	p. 321
Constrained Via Minimization and Signed Hypergraph Partitioning	p. 337
The Virtual Dimensions of a Straight Line Embedding of a Plane Graph	p. 357
Routing Around Two Rectangles to Minimize the Layout Area	p. 365
Table of Contents provided by Blackwell. All Rights Reserved.

Algorithmic Aspects of VLSI Layout

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