This book covers algorithms and applications of techniques from the artificial intelligence community in CAD for VLSI.
Expert assistance in digital circuit design, Z.M. Alvi and J.M. Noras; use of a theorem prover for transformational synthesis, A.M. Koelmans et al; an overview of high level synthesis technologies for digital ASICs, K.W. Turnbull; simulated annealing based synthesis of fast discrete cosine transform blocks, J.P. Neil and P.B. Denyer; knowledge based expert systems in testing and design for testability - an overview, G. Russell; knowledge based test strategy planning, C. Dislis et al; HIT - a hierarchical integrated test methodology, C.A. Njinda and W.R. Moore; use of fault augmented functions for automatic test pattern generation, N. Jeffrey et al; macro-test - a VLSI testable-design technique, F. Beenker and R.G. Bennetts; an expert systems approach to analogue VLSI layout synthesis, M.F. Chowdhury and R.E. Massara; guaranteeing optimality in a gridless router using AI techniques, M.F. Sharpe and R.J. Mack.
Series: I E E CIRCUITS, DEVICES AND SYSTEMS SERIES
Number Of Pages: 288
Publisher: Institution of Engineering and Technology
Country of Publication: GB
Dimensions (cm): 24.13 x 15.24
Weight (kg): 0.54