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Adaptive Techniques for Dynamic Processor Optimization : Theory and Practice - Alice Wang

Adaptive Techniques for Dynamic Processor Optimization

Theory and Practice

By: Alice Wang (Editor), Samuel Naffziger (Editor)

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Published: 11th June 2008
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This book is about various adaptive and dynamic techniques used to optimize processor power and performance. It is based on a very successful forum at ISSCC which focused on Adaptive Techniques.

The book looks at the underlying process technology for adaptive designs and then examines different circuits, architecture and software that address the different aspects. The chapters are written by people both in academia and the industry to show the scope of alternative practices.

Technology Challenges Motivating Adaptive Techniquesp. 1
Introductionp. 1
Motivation for Adaptive Techniquesp. 2
Components of Powerp. 2
Relation Between Frequency and Voltagep. 2
Control Loop Implementationp. 4
Practical Considerationsp. 4
Impact of Temperature and Supply Voltage Variationsp. 7
Technology Issues Relating to Performance-Enhancing Techniquesp. 9
Threshold Voltage Variationp. 9
Random Dopant Fluctuationsp. 11
Design in the Presence of Threshold Voltage Variationp. 13
Technology Issues Associated with Leakage Reduction Techniquesp. 14
Practical Considerationsp. 15
Sources of Leakage Currentp. 16
Transistor Design for Low Leakagep. 20
Conclusionp. 21
Referencesp. 21
Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuningp. 25
Adaptive Power Performance Tuning of ICsp. 25
AVS- and ABB-Scaling Operationsp. 28
Frequency Scaling and Tuningp. 31
Power and Frequency Tuningp. 33
Leakage Power Controlp. 37
Performance Compensationp. 40
Conclusionp. 44
Referencesp. 46
Adaptive Circuit Technique for Managing Power Consumptionp. 49
Introductionp. 49
Adaptive VDD Controlp. 50
Dynamic Voltage Scalingp. 50
Frequency and Voltage Hoppingp. 51
Adaptive VTH Controlp. 55
Reverse Body Bias (VTCMOS)p. 55
Self-Adjusting Threshold Voltage (SAT) Schemep. 55
Leakage Current Monitorp. 56
VTH Controllabilityp. 57
Device Perspectivep. 59
Forward Body Biasp. 60
Control Method and Granularityp. 61
VTH Control Under Variationsp. 64
VTH Control vs. VDD Controlp. 66
Hardware and Software Cooperative Controlp. 68
Cooperation Between Hardware and Application Softwarep. 68
Cooperation Between Hardware and Operating Systemp. 70
Conclusionp. 71
Referencesp. 71
Dynamic Adaptation Using Body Bias, Supply Voltage, and Frequencyp. 75
Introductionp. 75
Static Compensation with Body Bias and Supply Voltagep. 76
Adaptive Body Biasp. 77
Adaptive Supply Voltagep. 82
Dynamic Variation Compensationp. 84
Dynamic Body Biasp. 84
Dynamic Supply Voltage, Body Bias, and Frequencyp. 87
Design Detailsp. 87
Measurement Resultsp. 89
Conclusionp. 92
Referencesp. 92
Adaptive Supply Voltage Delivery for Ultra-Dynamic Voltage Scaled Systemsp. 95
Logic Design for U-DVS Systemsp. 97
Device Sizingp. 98
Timing Analysisp. 100
SRAM Design for Ultra Scalable Supply Voltagesp. 101
Low-Voltage Bit-Cell Designp. 104
Periphery Designp. 105
Intelligent Power Deliveryp. 107
Deriving VDD for Given Speed Requirementp. 107
DC-DC Converter Topologies for U-DVSp. 109
Linear Regulatorsp. 109
Inductor Based DC-DC Converterp. 109
Switched Capacitor Based DC-DC Converterp. 110
DC-DC Converter Design and Reference Voltage Selection for Highly Energy-Constrained Applicationsp. 112
Minimum Energy Tracking Loopp. 113
Conclusionp. 119
Referencesp. 120
Dynamic Voltage Scaling with the XScale Embedded Microprocessorp. 123
The XScale Microprocessorp. 123
Chapter Overviewp. 124
XScale Micro-Architecture Overviewp. 125
Dynamic Voltage Scalingp. 126
The Performance Measurement Unitp. 127
Dynamic Voltage Scaling on the XScale Microprocessorp. 129
Running DVSp. 130
Impact of DVS on Memory Blocksp. 134
Guaranteeing SRAM Stability with DVSp. 134
PLL and Clock Generation Considerationsp. 138
Clock Generation for DVS on the 180 nm 80200 XScale Microprocessorp. 138
Clock Generation 90 nm XScale Microprocessorp. 139
Conclusionp. 142
Referencesp. 142
Sensors for Critical Path Monitoringp. 145
Variability and its Impact on Timingp. 145
What Is a Critical Pathp. 147
Sources of Path Delay Variabilityp. 148
Process Variationp. 149
Environmental Variationp. 149
Timing Sensitivity of Path Delayp. 151
Critical Path Monitorsp. 158
Synchronizerp. 158
Delay Path Configurationp. 159
Time-to-Digital Conversionp. 163
Sensitivityp. 167
Control and Calibrationp. 168
Conclusionp. 169
Acknowledgementsp. 171
Referencesp. 171
Architectural Techniques for Adaptive Computingp. 175
Introductionp. 175
Spatial Reachp. 177
Temporal Rate of Changep. 177
"Always Correct" Techniquesp. 179
Look-up Table-Based Approachp. 179
Canary Circuits-Based Approachp. 180
In situ Triple-Latch Monitorp. 181
Micro-architectural Techniquesp. 182
Error Detection and Correction Approachesp. 183
Techniques for Communication and Signal Processingp. 184
Techniques for General-Purpose Computingp. 186
Introduction to Razorp. 187
Razor Error Detection and Recovery Schemep. 188
Micro-architectural Recoveryp. 190
Recovery Using Clock-Gatingp. 190
Recovery Using Counter-Flow Pipeliningp. 191
Short-Path Constraintsp. 192
Circuit-Level Implementation Issuesp. 192
Silicon Implementation and Evaluation of Razorp. 195
Measurement Resultsp. 196
Total Energy Savings with Razorp. 197
Razor Voltage Control Responsep. 199
Ongoing Razor Researchp. 200
Conclusionp. 202
Referencesp. 203
Variability-Aware Frequency Scaling in Multi-Clock Processorsp. 207
Introductionp. 207
Addressing Process Variabilityp. 209
Approachp. 209
Combinational Logic Variability Modelingp. 212
Array Structure Variability Modelingp. 213
Application to the Frequency Island Processorp. 215
Addressing Thermal Variabilityp. 217
Experimental Setupp. 218
Baseline Simulatorp. 218
Frequency Island Simulatorp. 219
Benchmarks Simulatedp. 219
Resultsp. 220
Frequency Island Baselinep. 220
Frequency Island with Critical Path Informationp. 221
Frequency Island with Thermally Aware Frequency Scalingp. 222
Frequency Island with Critical Path Information and Thermally Aware Frequency Scalingp. 224
Conclusionp. 225
Acknowledgementsp. 225
Referencesp. 225
Temporal Adaptation - Asynchronicity in Processor Designp. 229
Introductionp. 229
Asynchronous Design Stylesp. 230
Asynchronous Adaptation to Workloadp. 232
Data Dependent Timingp. 234
Architectural Variation in Asynchronous Systemsp. 237
Adapting the Latch Stylep. 237
Controlling the Pipeline Occupancyp. 240
Reconfiguring the Microarchitecturep. 241
Benefits of Asynchronous Designp. 244
Conclusionp. 245
Referencesp. 245
Dynamic and Adaptive Techniques in SRAM Designp. 249
Introductionp. 249
Read and Write Marginsp. 250
Voltage Optimization Techniquesp. 251
Column Voltage Optimizationp. 252
Row Voltage Optimizationp. 255
Timing Controlp. 257
Array Power Reductionp. 259
Sleep Typesp. 259
Active Sleepp. 260
Passive Sleepp. 261
P Versus N Sleepp. 263
Entering and Exiting Sleepp. 264
Dynamic Cache Power Downp. 266
Data Bus Encodingp. 266
Reliabilityp. 267
Soft Errorsp. 267
Hard Errorsp. 267
Cache Line Disablep. 268
Cache Line Remapp. 268
Defect Correctionp. 268
Conclusionp. 269
Referencesp. 270
The Challenges of Testing Adaptive Designsp. 273
The Adaptive Features of the Itanium 2 9000 Seriesp. 273
Active De-skewp. 273
Cache Safe Technologyp. 277
Foxton Technologyp. 278
The Path to Productionp. 281
Fundamentals of Testing with Automated Test Equipment (ATE)p. 281
Manufacturing Testp. 281
Class or Package Testingp. 283
System Testingp. 285
The Impact of Adaptive Techniques on Determinism and Repeatabilityp. 286
Validation of Active De-skewp. 287
Testing of Active De-skewp. 290
Testing of Power Measurementp. 291
Power Measurement Impacts on Other Testingp. 294
Test Limitations and Guard-Bandingp. 296
Guard-Band Concerns of Adaptive Power Managementp. 297
Conclusionp. 300
Referencesp. 300
Indexp. 303
Table of Contents provided by Ingram. All Rights Reserved.

ISBN: 9780387764719
ISBN-10: 0387764712
Series: Integrated Circuits and Systems
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 304
Published: 11th June 2008
Publisher: Springer-Verlag New York Inc.
Country of Publication: US
Dimensions (cm): 23.5 x 15.5  x 1.91
Weight (kg): 0.65