+612 9045 4394
Accelerating Test, Validation and Debug of High Speed Serial Interfaces - Yongquan Fan

Accelerating Test, Validation and Debug of High Speed Serial Interfaces

Hardcover Published: 29th November 2010
ISBN: 9789048193974
Number Of Pages: 194

Share This Book:


RRP $514.99
or 4 easy payments of $89.13 with Learn more
Ships in 7 to 10 business days

Other Available Editions (Hide)

  • Paperback View Product Published: 14th October 2014

High-Speed Serial Interface (HSSI) devices have become widespread in communications, from the embedded to high-performance computing systems, and from on-chip to a wide haul. Testing of HSSIs has been a challenging topic because of signal integrity issues, long test time and the need of expensive instruments. Accelerating Test, Validation and Debug of High Speed Serial Interfaces provides innovative test and debug approaches and detailed instructions on how to arrive to practical test of modern high-speed interfaces.

Accelerating Test, Validation and Debug of High Speed Serial Interfaces first proposes a new algorithm that enables us to perform receiver test more than 1000 times faster. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms, while the test usually takes seconds. The book also presents and external loopback-based testing scheme, where and FPGA-based BER tester and a novel jitter injection technique are proposed. These schemes can be applied to validate, test and debug HSSIs with data rate up to 12.5Gbps at a lower test cost than pure ATE solutions. In addition, the book introduces an efficieng scheme to implement high performance Gaussian noise generators, suitable for evaluating BER performance under noise conditions.

Introductionp. 1
Motivationp. 1
HSSI Technology Trendsp. 2
Qualification Challengesp. 5
ATE Perspectivesp. 6
Contributionsp. 8
Overview of the Bookp. 9
Backgroundp. 11
High-Speed Serial Communicationp. 11
HSSI Structurep. 14
BER Mechanismsp. 16
Jitter and Noise Impacts to BERp. 19
Timing Jitterp. 21
Jitter Overviewp. 21
Jitter and BERp. 23
Jitter Testingp. 26
Amplitude Noisep. 28
BER and SNRp. 28
Simulation and Emulationp. 33
AWGN Emulationp. 34
Accelerating Receiver Jitter Tolerance Testing on ATEp. 37
Introductionp. 38
Receiver Structure and Characteristicsp. 38
Jitter Tolerance Testing Overviewp. 44
Proposed New Methodp. 47
Jitter Test Signal Generationp. 51
Choosing Test Signal Parametersp. 52
Periodic Jitter Injectionp. 54
Creating Jitter-Free Data Signalp. 55
Creating a Digitized Jitter Signalp. 55
Modulating the Data Signalp. 56
Generating Bandwidth Limited Signalsp. 57
Downsampling to Get AWG Samplesp. 59
Fractional Samplingp. 60
Jitter Calibrationp. 61
Random Jitter Controlp. 64
Receiver Bit Error Monitoringp. 65
ATE-based Error Detectionp. 66
DFT-based Error Detectionp. 67
Jitter Tolerance Extrapolationp. 68
Jitter Tolerance Extrapolation Algorithmp. 69
Accelerating Jitter Tolerance Characterizationp. 72
Accelerating Jitter Tolerance Compliance Testingp. 79
Discussionp. 81
Other Applications of the New Methodp. 82
Jitter Transfer Characterizationp. 82
CDR Characteristics Analysisp. 84
Transmitter Jitter Extractions on ATEp. 87
Introductionp. 87
Transmitter Jitter Testing Overviewp. 88
Proposed Solutionp. 89
Test Setup for Data Acquisitionp. 90
Overview of the Test Setupp. 90
Principles of Clock Settingsp. 91
Test Setting Parameter Calculationsp. 93
Jitter Extractionp. 97
Generating Edge Displacementp. 98
Time Domain Approachp. 100
RJ Extractionp. 102
DJ Extractionp. 102
TJ Calculationp. 103
Frequency Domain Approachp. 107
RJ Extractionp. 107
DJ Extractionp. 108
Hybrid Approachp. 109
Limitations of Each Approachp. 111
Experimental Resultsp. 112
Bench Correlationp. 113
Correlating Two RJ Approachesp. 113
Impact of Test Patternsp. 115
Impact of the Reference Clockp. 116
Extending to 6 Gbps Applicationsp. 117
Summaryp. 118
Testing HSSIs with or without ATE Instrumentsp. 121
DFT in HSSIsp. 122
Internal BERTp. 122
Internal Loopbackp. 123
Other DFT Techniquesp. 124
Limitations of DFTsp. 125
FPGA-based Bit Error Detectionp. 125
Implementing a Serial BERTp. 126
Implementing a Parallel BERTp. 128
HSSI Testing Demonstrationp. 129
Loopback Testing with Jitter Injectionp. 130
Testing Setupp. 130
Phase Delay Based jitter Injectionp. 131
Experimental Resultsp. 134
A Versatile HSSI Testing Schemep. 137
Major Functions of our Setupp. 138
Testing, Validation and Debugging on ATEp. 138
External Loopback with Jitter Injectionp. 139
Other Configurationsp. 140
High Speed Relaysp. 141
Limitations and Further Considerationsp. 146
BER Testing Under Noisep. 149
AWGN Generation Overviewp. 149
Existing Methodsp. 150
CLT Methodp. 150
Box-Muller Methodp. 150
Mixed Methodp. 151
Cellular Automata Based Methodp. 152
Analog Methodp. 153
Our Methodp. 153
Our Implementationp. 155
Generating Random Variablesp. 155
One Bit Random Number Generatorp. 155
Multiple-Bit Random Number Generatorp. 158
Gaussian Variable Generationp. 159
Implementing a Single Generatorp. 159
Implementing Two Generatorsp. 163
Accuracy Improvementp. 164
Statistical Properties of our AGWN Generatorp. 165
Q(x) Evaluationp. 165
Kurtosis Valuep. 168
Baseband Transmission Testingp. 169
Baseband Signal Formatsp. 169
SNR Settingp. 171
Testing Setup and Resultsp. 172
Advantages of Our AWGN Generatorp. 176
Conclusionsp. 179
Referencep. 183
Indexp. 193
Table of Contents provided by Ingram. All Rights Reserved.

ISBN: 9789048193974
ISBN-10: 9048193974
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 194
Published: 29th November 2010
Publisher: Springer
Country of Publication: NL
Dimensions (cm): 23.5 x 15.5  x 1.91
Weight (kg): 1.04