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High Level Synthesis of ASICs Under Timing and Synchronization Constraints : Recent Economic Thought - David C. Ku

High Level Synthesis of ASICs Under Timing and Synchronization Constraints

Recent Economic Thought


Published: 31st May 1992
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Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

Introductionp. 1
Overview of High-level Synthesisp. 2
Motivation and Issues in High-level Synthesisp. 3
Research Objectivesp. 6
Summary of Related Workp. 13
Assumptions and Limitationsp. 16
Outline of the Bookp. 16
System Overviewp. 19
Modeling Hardware Behaviorp. 19
Overview of the Synthesis Flowp. 42
Behavioral Transformationsp. 47
Behavioral Intermediate Formp. 48
User-driven Behavioral Transformationsp. 49
Automatic Behavioral Transformationsp. 51
Summary of Behavioral Transformationsp. 60
Sequencing Graph and Resource Modelp. 61
Basic Definitionsp. 62
Timing Constraintsp. 69
Hardware Resourcesp. 75
Summary of Sequencing Graph Modelp. 80
Design Space Explorationp. 83
Design Space Formulationp. 85
Concurrency Factorp. 93
Design Space Exploration Strategyp. 102
Summary of Design Space Explorationp. 110
Relative Schedulingp. 113
Introduction to Schedulingp. 117
Relative Scheduling Formulationp. 118
Algorithms for Relative Schedulingp. 141
Analysis of Algorithmsp. 156
Summary of Relative Schedulingp. 161
Resource Conflict Resolutionp. 163
Conflict Resolution Formulationp. 164
Constraint Topologyp. 166
Algorithms for Conflict Resolutionp. 174
Summary of Conflict Resolutionp. 181
Relative Control Generationp. 183
Adaptive Control Approachp. 187
Relative Control Approachp. 204
Summary of Control Generationp. 212
Relative Control Optimizationp. 213
Control Optimization Criterionp. 214
Redundancy in Synchronizationp. 217
Control Optimization Approachp. 223
Analysis of Control Resynchronizationp. 234
Summary of Control Resynchronizationp. 235
System Implementationp. 237
Overview of Herculesp. 239
Overview of Hebep. 243
Summary of System Implementationp. 252
Experimental Resultsp. 253
Design Experiencesp. 254
Synthesis of Benchmark Examplesp. 270
Summary of Experimental Resultsp. 273
Conclusions and Future Workp. 275
Future Workp. 277
Referencesp. 281
Indexp. 291
Table of Contents provided by Blackwell. All Rights Reserved.

ISBN: 9780792392446
ISBN-10: 0792392442
Series: Recent Economic Thought
Audience: Professional
Format: Hardcover
Language: English
Number Of Pages: 308
Published: 31st May 1992
Country of Publication: US
Dimensions (cm): 23.39 x 15.6  x 1.91
Weight (kg): 0.61