Hardware correctness is becoming ever more important in the design of computer systems. The authors introduce a powerful new approach to the design and analysis of modern computer architectures, based on mathematically well-founded formal methods which allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation. This book develops, at the gate level, the complete design of a pipelined RISC processor with a fully IEEE-compliant floating-point unit. In contrast to other design approaches, the design presented here is modular, clean and complete.
| Introduction | |
| Basics | |
| A Sequential DLX Design | |
| Basic Pipelines | |
| Interrupt Handling | |
| Memory System Design | |
| IEEE Standard | |
| Floating Point Algorithms & Data Paths | |
| Pipelined DLX with FPU | |
| DLX Instruction Set Architecture | |
| Specification of the FDLX Design | |
| Bibliography | |
| Index | |
| Table of Contents provided by Publisher. All Rights Reserved. |
ISBN: 9783540674818
ISBN-10: 3540674810
Audience:
Tertiary; University or College
Format:
Hardcover
Language:
English
Number Of Pages: 572
Published: 16th June 2000
Dimensions (cm): 25.4 x 17.8
x 3.1
Weight (kg): 1.202